COMMENT *
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SDSUII Timing Board DSP code for EEV42-90 single output - CFHT's DetI
--------------------------------------------------------------------------------
DetI Initial revision: Oct. 1998 - J.-C. Cuillandre (CFHT) jcc@cfht.hawaii.edu
-> Based on Rev. 3.00 file provided by B. Leach
-> ltb_CCID20.asm runs 2 CCDs MIT/LL CCDI20 2Kx4K
-> Detector readout routine supports binning and sub-rastering
-> Implementation of the dithering anti-blooming (with option bit)
-> Generation of a test pattern to check system not using SXMIT
-> Enhanced code readability
-> IDLE mode disabled
--------------------------------------------------------------------------------
EEV42-90 initial revision: ....
; Based on ltb_CCID20.asm to read two CCDs
; Initial revision - jamey@cfht.hawaii.edu - 04/99
; This file contains the waveforms for reading out the EEV42-90 CCD in
; single readout mode of the Left or Right amplifier.  It also contains
; the different VDELAY and gain settings for reading out on Gecko (250 columns
; x 4608 rows), and for normal full frame readout, 2048 x 4608.
; The linearity is less then 0.5% for both settings, while the noise
; for Gecko is < 4 electrons, and full frame is between 5 and 6 electrons.
;===============================================================================
This file is used to generate DSP code for the second generation timing board. 

This is Rev. 3.00 software.     

Timing modified for Datel A/D converter starting 11-6-96
Modified for timing board Rev. 4B Feb. 17, 1997
Put rarely used and non-time critical routines in SRAM program memory (P:>$200)

-d DOWNLOAD 1	To generate code for downloading to DSP memory.
-d DOWNLOAD 0	To generate code for writing to the EEPROM.

Information from the EEV 42-90 chip:  :

                               P->   1          
     4.5K lines imaging        P->   2      
                               P->   3      
                                  --------
                 4 pre-scan pixels 
             <------------------->|     |  |     |
      |OG|SW|S2|S1|S3|...|S2|S1|S3|S2|S1|S3|S2|S1|S3|..|S3|S2|S1|SW|OG|
        |
        |     OD
       _|_   _|
     _|   |_|
 RG-|_      |_
      |       |
      RD      SO

 LEFT output on this side                          RIGHT output (same structure)
To go from one output to the other, switch DAC address for S1 and S2
	*
	PAGE    132     ; Printronix page width - 132 columns

;===============================================================================
; Define a section name so it doesn't conflict with other application programs
	SECTION	EEV1E

; These are also defined in "timboot.asm", so be sure they agree
APL_NUM	EQU	0	; Application number from 0 to 3
APL_ADR	EQU	$10A	; P: memory location where application code begins
APL_LEN	EQU	$200-APL_ADR ; Maximum length of application program
COM_TBL EQU     $80     ; Starting address of command table in X: memory
N_W_APL	EQU	$500	; Number of words in each application

; Board status bits, defined at X:<STATUS = X:0
IDLING  EQU     0	; Set if in idle mode => clocking out
IDLMODE	EQU	1	; Set if need to idle after readout
ST_RDC	EQU	4	; Set if executing 'RDC' command - reading out

; board OPTIONS bits, defined at Y:<OPTIONS = Y:0
; first bit: 0
TSTPAT  EQU     1       ; DetI : set if incremented data pattern required
CNTPAT  EQU     2       ; DetI : set if constant pattern required
TURBO   EQU     3       ; DetI : set if very high readout speed required
ABLDT   EQU     4       ; DetI : set if dithering antiblooming required 4

; Define some timing board addresses
WRLATCH	EQU	$FFC1	; Write to timing board latch
WRFO	EQU	$FFC0	; Write to fiber optic transmitter
SSITX	EQU	$FFEF	; SSI Transmit and Receive data register
SSISR	EQU	$FFEE	; SSI Status Register
PBD	EQU	$FFE4	; Port B Data Register
PCC     EQU     $FFE1   ; Port C Control Register
PCDDR	EQU	$FFE3	; Port C Data Direction Register
PCD     EQU     $FFE5   ; Port C Data Register
BCR     EQU     $FFFE   ; Bus (=Port A) Control Register -> Wait States
RSTWDT	EQU	$6000	; Address to reset the timing board watchdog timer

; ADC addressing code
ADCQ1	EQU	$FFA0   ; Address for reading A/D Q1
ADCQ2	EQU	$FFA1   ; Address for reading A/D Q2
ADCQ3	EQU	$FFA2   ; Address for reading A/D Q3
ADCQ4	EQU	$FFA3   ; Address for reading A/D Q4
ADCQ5	EQU	$FFA4   ; Address for reading A/D Q5
ADCQ6	EQU	$FFA5   ; Address for reading A/D Q6

; Define mosaic quadrant (output) selection codes QUAD=0x3F for all 6 quadrants
Q1      EQU     0       ; Quadrant 1 QUAD=0x01
Q2      EQU     1       ; Quadrant 2 QUAD=0x02
Q3      EQU     2       ; Quadrant 3 QUAD=0x04
Q4      EQU     3       ; Quadrant 4 QUAD=0x08
Q5      EQU     4       ; Quadrant 5 QUAD=0x10
Q6      EQU     5       ; Quadrant 6 QUAD=0x20

; All video boards with same SWITCH jumpers configuration: 1 add for all
VIDEO   EQU     $000000 ; Video processor board select All

; Video board bias DAC selection - individual board selection
; Jumper configuration for DACs is as follow (4 jumpers bank 0->3, X for SET):
; DAC Jumpers:    0       1       2       3       Address
; Video1 ID0:     X       X       X       X       0000
; Video2 ID1:             X       X       X       1000
; Video3 ID2:     X               X       X       2000
BIAS1	EQU	$000000	; Video processor board #1
BIAS2	EQU	$001000	; Video processor board #2

; Board clocking bank selection - bank1={clk 0 -> 11} bank2={clk 11 -> 23}
; DUAL mode set, only bank1 needs to be addressed
; All clocking boards with same SWITCH jumpers configuration: 1 add for all
; SWITCH jumpers must be for address $004000:
; SWITCH Jumpers:    1       2       3       Address
; like DAC1 =>       X               X       4000
CLK	EQU	$002000	; Clock driver all boards (same as DAC1 - ID4)

; Board clocking DAC selection - individual board selection
; Jumper configuration for DACs is as follow (4 jumpers bank 0->6, X for SET):
; There are two banks per board, system knows that +1 as to be added.
; DAC Jumpers:    0       1       2       3       Address
; Clock1 ID4:     X       X               X       4000
; Clock2 ID6:     X                       X       6000
; Clock3 ID8:     X       X       X               8000 
DAC1	EQU	$002000	; Clock driver board #1 select = ID4 for bank 1
;DAC1	EQU	$004000	; Clock driver board #1 select = ID4 for bank 1
;DAC2	EQU	$006000	; Clock driver board #2 select = ID6 for bank 1
DAC3	EQU	$008000	; Clock driver board #3 select = ID8 for bank 1

; Delays ! Only the first two digits over the six. MAX=5.8us
; ! Non linear scale: 16=0.5 23=0.8 2F=1us BC=10us FF=20us 
PDELAY	EQU	$FF0000 ; Parallel clock delay = 5.8 microsec
SDELAY	EQU	$200000	; Serial   clock delay = 0.4 microsec was 20
RDELAY	EQU	$070000	; Reset    clock delay = 0.2 microsec
; Full frame setting
;VDELAY	EQU	$2D0000	; Video integration time = 1.0 microsec
; Gecko slow readout setting
VDELAY	EQU	$B80000	; Video integration time = 9.1 microsec
NDELAY	EQU	$000000	; No Delay

; Bias voltage definition
GAININT	EQU	$C3000	; Gain and integration speed
INOFFA	EQU	$C0000	; Input offset for channel A
INOFFB	EQU	$C8000	; Input offset for channel B
OUTOFFA EQU     $C4000  ; Input offset for channel A
OUTOFFB EQU     $CC000  ; Input offset for channel B

; Define DC bias voltages
;----------------------------------------------------------
; Name          Address   Bias  Description 	CCD	Pin
;----------------------------------------------------------
VODL	EQU	$D0000  ; VOD = Output Drain     A 	 1
VODR    EQU     $D4000  ; VOD = Output Drain     B 	 2
VRDL	EQU	$D8000	; VRD = Reset Drain      A 	 3
VRDR    EQU     $DC000  ; VRD = Reset Drain      B       4	
VDD    	EQU     $E0000  ; VDD = Dump Drain 	 A 	 5
VOG1	EQU	$F0000	; VOG = Output Gate      A 	 9
VOG2    EQU     $F4000  ; VOG = Output Gate      B 	10
;----------------------------------------------------------

; Switch state bits for the CCD A & B clocks -> both banks (synchroneous)
;---------------------------------------------------------------------------------
; Signal  ---  DAC ---   Pin bank A - Pin bank B - Description
;---------------------------------------------------------------------------------
RGL    	EQU     0       ;   1        	- Reset output node
RGH    	EQU     $1
S1LL   	EQU     0       ;   2 		- Serial register, phase 1 Left
S1LH  	EQU     $2
S1RL   	EQU     0       ;   3 	 	- Serial register, phase 1 Right
S1RH   	EQU     $4
S2LL   	EQU     0       ;   4 	 	- Serial register, phase 2 Left
S2LH   	EQU     $8
S2RL  	EQU     0       ;   5 		- Serial register, phase 2 Right
S2RH  	EQU     $10
S3L  	EQU     0       ;   6 		- Serial register, phase 3
S3H  	EQU     $20
SWLL  	EQU     0       ;   7 		- Summing well Left
SWLH  	EQU     $40
SWRL  	EQU     0       ;   8       	- Summing well Right
SWRH  	EQU     $80
P1L  	EQU     0       ;   9        	- Parallel register phase 1
P1H  	EQU     $100
P2L  	EQU     0       ;  10           - Parallel register phase 2
P2H  	EQU     $200
P3L  	EQU     0       ;  11           - Parallel register phase 3
P3H  	EQU     $400
DGL  	EQU     0       ;  12           - Dump Gate
DGH  	EQU     $800
;---------------------------------------------------------------------------------

; CCD clock voltage definitions
; Range: -10V ($000) -> +10V ($FFF) ~ $CC per volt
;--------------------------------------------------------------
; Name 		Value	Description		Voltage (volts)
;--------------------------------------------------------------
;Settings for using logic analyzer, 0 to +5V
;R_HI    EQU     $C00    ; Reset clock High 	+05.0
;R_LO    EQU     $800    ; Reset clock Low  	0.0
;S_HI	EQU	$C00	; Serial clocks High 	+05.0
;S_LO	EQU	$800	; Serial clocks Low  	0.0
;W_HI    EQU     $C00    ; Summing Well High 	+05.0
;W_LO    EQU     $800    ; Summing Well Low  	0.0
;P_HI	EQU	$C00	; Parallel High 	+05.0
;P_LO	EQU	$800	; Parallel Low  	0.0
;--------------------------------------------------------------
R_HI    EQU     $D60    ; Reset clock High 	+6.80
R_LO    EQU     $700    ; Reset clock Low  	-1.20
;S_HI	EQU	$C00	; Serial clocks High 	+5.00	
;S_LO	EQU	$400	; Serial clocks Low  	-5.00
S_HI	EQU	$D80	; Serial clocks High 	 D00 fixes CTE prob. (not the trap)
S_LO	EQU	$180	; Serial clocks Low  	 280 fixes CTE prob. (not the trap)
W_HI    EQU     $C00    ; Summing Well High 	+5.00
W_LO    EQU     $400    ; Summing Well Low  	-5.00
P_HI	EQU	$99A	; Parallel High 	+2.00
P_LO	EQU	$335	; Parallel Low  	-6.00

; Misc definitions
WW	EQU	1	; Word width = 1 for 16-bit image data, 0 for 24-bit
CDAC	EQU	0	; Bit number in U25 for clearing DACs
DUALCLK	EQU	1	; Set to clock two halves of clock driver board together
ENCK	EQU	2	; Bit number in U25 for enabling analog switches
SYNC    EQU     11      ; Master/Slave synchronization bit

; SXMIT values: for use with GenII host system only
SXMIT	EQU     $00F021
; $00F0A0	Series transmit A/D channels #0 to #5
; $00F060	Series transmit A/D channels #0 to #3
; $00F020	Series transmit A/D channels #0 to #1
; $00F062	Series transmit A/D channels #2 to #3
; $00F000	Series transmit A/D channel  #0
; $00F021	Series transmit A/D channel  #1
; $00F042	Series transmit A/D channel  #2
; $00F063	Series transmit A/D channel  #3
; $00F084	Series transmit A/D channel  #4
; $00F0A5	Series transmit A/D channel  #5

;**************************************************************************
;                   	                                                  *
;    Permanent address register assignments                               *
;	 S1 - Address of SSI receiver contents				  *
;	 S2 - Address of SCI receiver contents				  *
;        S3 - Pointer to current top of command buffer                    *
;        R4 - Pointer to processed contents of command buffer		  *
;        R5 - Temporary register for processing SSI and SCI contents      *
;        R6 - CCD clock driver address for CCD #0 = $FF80                 *
;                It is also the A/D address of analog board #0            *
;                                                                         *
;    Other registers                                                      *
;        R0, R7 - Temporary registers used all over the place.            *
;        R5 - Can be used as a temporary register but is circular,        *
;               modulo 32.       					  *
;**************************************************************************

;  Specify execution and load addresses
	IF	DOWNLOAD
	ORG	P:APL_ADR,P:APL_ADR		; Download address
	ELSE
	ORG     P:APL_ADR,P:APL_NUM*N_W_APL	; EEPROM address
	ENDIF

;===============================
;== MASTER/SLAVE TIMING BOARD ==
;===============================
; Master timing board. First lines must match boot code (ltb_masterboot.asm)
IDLE    JMP	<START		; IDLE not implemented
RDDET	JMP	<RD_DET		; Read detector

;============
;== DITHER ==
;============
; Dithering between P1<->P2 during integration (dithering antiblooming)
DITHER  MOVE    #<DTHP2,R0      ; Move electrons under P2
        JSR     <CLOCK          ; Go clock out the detector charge
        JSR     <WAIT           ; Delay
        MOVE    #<DTHP1,R0      ; Move electrons under P1
        JSR     <CLOCK          ; Go clock out the detector charge
        JSR     <WAIT           ; Delay
        JSR     <GET_RCV        ; Check for FO or SSI commands
        JCC     <NO_CMD         ; Continue dithering if no commands received
        JMP     <CHK_SSI        ; Go process header and command
NO_CMD  JMP     <DITHER

;============
;=== WAIT ===
;============
; Slow delay for use with dithering antiblooming
WAIT    DO      Y:<DELABL,EWAIT  ; DELABL defines pump frequency
        DO      #$F5,SUBW        ; this loop is 10us long
        NOP                      ; one NOP makes a 41ns delay
SUBW    NOP                      ; do not use REP #x because bug
EWAIT   RTS

;===========
;== CLEAR ==
;===========
; Fast clear image before each exposure
CLEAR	DO	#1000,LPCLR	; Loop to clear the array before exp.

	DO      #20,LPCLR2	; Loop over number of lines in image
	MOVE    #<PXFERDUMP,R0	; Address of parallel transfer waveform
	JSR     <CLOCK  	; Go clock out the CCD charge
	NOP			; Do loop restriction
LPCLR2
	DO      Y:NSCLR,LSCLR1
        MOVE    #<SSKIP,R0
        JSR     <CLOCK
        NOP
LSCLR1
	NOP
LPCLR

        MOVE    #<INTG,R0
        JSR     <CLOCK
        NOP

; If no dithering anti-blooming requested, go to FINISH now
	JCLR    #ABLDT,Y:<OPTIONS,FINISH

; Send DON back before dithering P1 and P2
; CLR might come from host also, check who the sender is
        MOVE    X:<HDR,A     	; Get header of incoming command
        MOVE    X:<SMASK,Y0     ; This was the source byte, and is to
        AND     Y0,A  X:<TWO,Y0 ; become the destination byte
        REP     #8              ; Shift right one byte, add it to the header
        LSR     A
        ADD     Y0,A  X:<SBRD,Y0
        ADD     Y0,A            ; Add source board ID (header for host = 020002)
	MOVEP   A,Y:WRFO        ; Send it down the fiber
        DO      #40,DLY_FBR     ; Delay for the serial transmitter
        NOP
DLY_FBR
        MOVE    X:<DON,A        ; Load DON
	MOVEP   A,Y:WRFO        ; Send it down the fiber

; Dither electrons between P1 and P2
        JMP     <DITHER

;============
;== RD_DET ==
;============
; Read detector
RD_DET	BSET    #ST_RDC,X:<STATUS ; Set status to reading out
        BSET    #WW,X:PBD       ; Set WW = 1 for 16-bit image data

; reset incremental value for the test pattern
	CLR	A
        MOVE    A,Y:<TSTVAL

; Setup clocks to evacuate exceding charges
        MOVE    #<SREV,R0
        JSR     <CLOCK

; Skip over NPSKIP lines if necessary
        MOVE    Y:<NPSKIP,A
        TST     A
        JEQ     <NOPSKIP
        DO      A,LPSKIP
;        MOVE    #<PXFER,R0
        MOVE    #<PXFERDUMP,R0
        JSR     <CLOCK
        NOP
LPSKIP

; Clear serial register after parallel skip, set serials to accept charge
NOPSKIP DO      Y:NSCLR,LSCLR
        MOVE    #<SSKIP,R0
        JSR     <CLOCK
        NOP
LSCLR

; If full detector readout, add NPOVR to NPR (NPOVR reset by DetI if not)
        MOVE    Y:<NPOVR,A
        MOVE    Y:<NPR,B
        ADD     A,B
        MOVE    B,Y:<TNPR

; Start the loop for parallel shifting desired number of lines
        DO      Y:<TNPR,LPR     ; Loop over each line readout

; Parallel clock shift - move the image into the serial shift register
; one line at a time
        DO      Y:<NPBIN,LPBIN  ; Loop over parallel shifting
        MOVE    #<PXFER,R0      ; Address of parallel clocking waveform
        JSR     <CLOCK          ; Go clock out the detector charge
        NOP
LPBIN

; Skip over PRESCAN pixels - we have some for sure on MIT/LL CCDs
        MOVE    Y:<NSPRE,A      ;
        DO      A,DOSKIP        ; Loop over number of pixels to skip
        MOVE    #<SSKIP,R0      ; Address of parallel transfer waveform
        JSR     <CLOCK          ; Go clock out the detector charge
        NOP                     ; Do loop restriction
DOSKIP

; Skip over NSSKIP pixels if necessary
        MOVE    Y:<NSSKIP,A     ; If NSSKIP = 0 then don't skip
        TST     A
        JEQ     <NOSSKIP
        DO      A,LSSKIP        ; Loop over number of pixels to skip
        MOVE    #<SSKIP,R0      ; Address of parallel transfer waveform
        JSR     <CLOCK          ; Go clock out the detector charge
        NOP                     ; Do loop restriction
LSSKIP

; Test pattern: TSTPAT bit in X:<OPTIONS
NOSSKIP JCLR    #TSTPAT,Y:<OPTIONS,ADCREAD
	DO      Y:<NSR,LSRTP    ; Loop over number of pixels per line
        JSR     <SNDTP
	NOP
LSRTP
        JMP     <LSR

; Read NSR pixels - serial clock shift
ADCREAD DO      Y:<NSR,LSR      ; Loop over number of pixels per line
        MOVE    #<RSTNODE,R0    ; First reset the output node
        JSR     <CLOCK          ; Go to it
        DO      Y:<NSBIN,LSBIN  ; Loop over binning parameter
        MOVE    #<SXFER,R0      ; Get serial transfer address
        JSR     <CLOCK          ; Go do serial pixel transfer
        NOP                     ; DO loop restriction
LSBIN
        MOVE    #<VPROC,R0      ; Do the video processing
        JSR     <CLOCK          ; Go to it
	NOP
LSR                             ; End of loop label for serial register
        
; Skip over NSSKIP2 pixels - will clear remaining of serial register for sure
        MOVE    Y:<NSSKIP2,A    ; If NSSKIP2 = 0 then don't skip
        TST     A
        JEQ     <NOVSKIP
        DO      A,LSSKIP2       ; Loop over number of pixels per line
        MOVE    #<SSKIP,R0      ; Get serial transfer address
        JSR     <CLOCK          ; Go do serial pixel transfer
        NOP                     ; DO loop restriction
LSSKIP2                   	; End of loop label for serial register

; Read NSOVR pixels - serial clock shift - only in full frame mode (DetI)
NOVSKIP MOVE    Y:<NSOVR,A      ; If NSOVR = 0 then don't read
        TST     A
        JEQ     <LSROVR

; Test pattern: TSTPAT bit in X:<OPTIONS
        JCLR    #TSTPAT,Y:<OPTIONS,ADCOV
	DO      Y:<NSOVR,LSROVTP ; Loop over number of overscan pixels
        JSR     <SNDOTP
	NOP
LSROVTP
        JMP     <LSROVR

ADCOV   DO      Y:<NSOVR,LSROVR ; Loop over number of overscan pixels
        MOVE    #<RSTNODE,R0    ; First reset the output node
        JSR     <CLOCK          ; Go to it
        DO      Y:<NSBIN,LSBIN3 ; Loop over binning parameter
        MOVE    #<SXFER,R0      ; Get serial transfer address
        JSR     <CLOCK          ; Go do serial pixel transfer
        NOP                     ; DO loop restriction
LSBIN3
        MOVE    #<VPROC,R0      ; Do the video processing
        JSR     <CLOCK          ; Go to it
	NOP
LSROVR  NOP                     ; End of loop label for overscan serial register

LPR                             ; End of loop label for parallel register

; !!!!! Skip over lines that aren't read out each time.... 4500 - 4016 = 484
; This is a patch until the VME code is fixed....

;        DO      Y:<EPS,LPSKIP2
        DO      #484,LPSKIP2
        MOVE    #<PXFER,R0
        JSR     <CLOCK
        NOP
LPSKIP2


; All done, set parallels to inversion
        MOVE    #<INVR,R0        ; Put Parallels in inversion
        JSR     <CLOCK

; Wait for a new command
	BCLR	#WW,X:PBD	; Clear WW to 0 for 32-bit commands
	BCLR	#ST_RDC,X:<STATUS ; Clear status to reading out

	RTI			; Long interrupt return for synchronization
				; go back to RD_IRQ

;============
;== RD_IRQ ==
;============
; Generate an interrupt request to begin readout - will go to RDDET and return
RD_IRQ	BCLR    #SYNC,X:PBD     ; Toggle SYNC bit
	BSET    #SYNC,X:PBD

        JMP     <START		; Wait for a new command

;============
;== FBRSND ==
;============
; Sent data to fiber, then delay after sending a pixel down the fiber.
FBRSND  MOVEP   A,Y:WRFO        ; Send it down the fiber
	REP     Y:<FBRDLY
        NOP
        RTS

;===========
;== CLOCK ==
;===========
; Core subroutine for clocking out CCD charge
CLOCK   MOVE    Y:(R0)+,X0      ; # of waveform entries 
        MOVE    Y:(R0)+,B       ; Start the pipeline
        DO      X0,CLKL                 ; Repeat X0 times
        MOVE    B,X:(R6) Y:(R0)+,B      ; Send out the waveform
	NOP
CLKL
        MOVE    B,X:(R6)        ; Flush out the pipeline
        RTS                     ; Return from subroutine

;===============================================================================
; Check for program overflow
        IF	@CVS(N,*)>=$200
        WARN    'Application P: program is too large!'	; Make sure program
	ENDIF						;  will not overflow
;===============================================================================

; ****************  PROGRAM CODE IN SRAM PROGRAM SPACE    *******************
; Put all the following code in SRAM (don't put code needing speed performances
; here), starting at P:$200.
	IF	DOWNLOAD
	ORG	P:$200,P:$200	; Download address
	ELSE
	ORG	P:$200,P:APL_NUM*N_W_APL+APL_LEN ; EEPROM address
	ENDIF

;===========
;== SNDTP ==
;===========
; Send out test pattern data over the fiber - imaging area
SNDTP   MOVE    X:<ONE,X0       ; Load X with 1
        MOVE    Y:<TSTVAL,A     ; Load A with test pattern value
	JCLR	#Q1,Y:<QUAD,SNDTP_A
	JSR     <FBRSND         ; Send it down the fiber
SNDTP_A	ADD	X0,A		; Increment Test pattern value
	JCLR	#Q2,Y:<QUAD,SNDTP_B
	JSR     <FBRSND         ; Send it down the fiber
SNDTP_B	ADD	X0,A		; Increment Test pattern value
	JCLR	#Q3,Y:<QUAD,SNDTP_C
	JSR     <FBRSND         ; Send it down the fiber
SNDTP_C	ADD	X0,A		; Increment Test pattern value
	JCLR	#Q4,Y:<QUAD,SNDTP_D
	JSR     <FBRSND         ; Send it down the fiber
SNDTP_D ADD     X0,A            ; Increment Test pattern value
        JCLR    #Q5,Y:<QUAD,SNDTP_E
	JSR     <FBRSND         ; Send it down the fiber
SNDTP_E ADD     X0,A            ; Increment Test pattern value
        JCLR    #Q6,Y:<QUAD,SNDTP_F
	JSR     <FBRSND         ; Send it down the fiber
SNDTP_F	JSET    #CNTPAT,Y:<OPTIONS,SNDTPEND
	MOVE    Y:<SEED,X0      ; Load X with test pattern increment
        MOVE    Y:<TSTVAL,A     ; Load A with test pattern value
        ADD     X0,A            ; Increment Test pattern value
        MOVE    #$FFFF,Y0
        CMP     Y0,A
        JLE     N_TPRST
        CLR	A		; Reset test pattern value
N_TPRST	MOVE	A,Y:<TSTVAL	; Store updated value in memory
SNDTPEND	
	RTS

;============
;== SNDOTP ==
;============
; Send out constant data (1) over the fiber - overscan area
SNDOTP  MOVE    Y:<TSTOV,A	; Load A with overscan fake value
	JCLR	#Q1,Y:<QUAD,TPOV_A
	JSR     <FBRSND         ; Send it down the fiber
TPOV_A	JCLR	#Q2,Y:<QUAD,TPOV_B
	JSR     <FBRSND         ; Send it down the fiber
TPOV_B	JCLR	#Q3,Y:<QUAD,TPOV_C
	JSR     <FBRSND         ; Send it down the fiber
TPOV_C	JCLR	#Q4,Y:<QUAD,TPOV_D
	JSR     <FBRSND         ; Send it down the fiber
TPOV_D  JCLR    #Q5,Y:<QUAD,TPOV_E
	JSR     <FBRSND         ; Send it down the fiber
TPOV_E  JCLR    #Q6,Y:<QUAD,TPOV_F
	JSR     <FBRSND         ; Send it down the fiber
TPOV_F	NOP
	RTS

;=================
;== IDL and STP ==
;=================
; IDLE mode not active on the CFH12K - Put here for some compatibilities
IDL	NOP
STP     BCLR    #IDLING,X:<STATUS
        JMP     <FINISH

;=========
;== WHO ==
;=========
; This returns dsp code ID
WHO     MOVE    Y:<DET,X0
        JMP     <FINISH1

;=============
;== SET_DAC ==
;=============
;  Update the DACs
SET_DAC MOVE    Y:(R0)+,X0              ; Get the number of table entries
        DO      X0,SET_L0               ; Repeat X0 times
        MOVEP   Y:(R0)+,X:SSITX         ; Send out the waveform
        JSR     <PAL_DLY                ; Wait for SSI and PAL to be empty
        NOP                             ; Do loop restriction
SET_L0
        RTS                             ; Return from subroutine

;=============
;== SETBIAS ==
;=============
; Set all the DC bias voltages and video processor offset values, reading
; them from the table labeled DACS in this file
SETBIAS JSR     <SER_ANA
        BSET    #CDAC,X:<LATCH          ; Disable clearing of DACs
        BSET    #DUALCLK,X:<LATCH       ; Enable parallel switching of clocks
        BSET    #ENCK,X:<LATCH          ; Enable clock and DAC output switches
        MOVEP   X:LATCH,Y:WRLATCH       ; Disable clear of DAC and enable clocks
        JSR     <PAL_DLY                ; Delay for all this to happen
        JSR     <PAL_DLY                ; Delay for all this to happen

; Read DAC values from a table, and set DACs
        MOVE    #DACS,R0        ; Get starting address of DAC values
        JSR     <SET_DAC

; Set all video processor analog switches to open to disable them (1 => OFF)
        MOVE    #$000FFF,A
        MOVE    A,X:(R6)        ; Send out the waveform
        NOP

; Let the DAC voltages all ramp up before exiting
        MOVE    #400,A          ; Delay 4 millisec
        DO      A,L_SBV1
        JSR     <PAL_DLY        ; Delay for all this to happen
        NOP
L_SBV1
        JSR     <SER_UTL        ; Return SSI to utility board communication
        JMP     <FINISH

;=============
;== PAL_DLY ==
;=============
; Delay for serial writes to the PALs and DACs by 8 microsec
PAL_DLY DO      #250,DLY         ; Wait 8 usec for serial data transmission
        NOP
        NOP
DLY     NOP
        RTS

;=============
;== ST_GAIN ==
;=============
; Set the video processor gain and integrator speed for all video boards
; Command syntax is  SGN  #GAIN  #SPEED, #GAIN = 1, 2, 5 or 10	
; #SPEED = 0 for slow, 1 for fast
ST_GAIN	JSR	<SER_ANA	; Set SSI to analog board communication
	MOVE	X:(R4)+,A	; Gain value (1,2,5 or 10)
	MOVE	#>1,X0
	CMP	X0,A		; Check for gain = x1
	JNE	<STG2
	MOVE	#>$77,B
	JMP	<STG_A
STG2	MOVE	#>2,X0		; Check for gain = x2
	CMP	X0,A
	JNE	<STG5
	MOVE	#>$BB,B
	JMP	<STG_A
STG5	MOVE	#>5,X0		; Check for gain = x5
	CMP	X0,A
	JNE	<STG10
	MOVE	#>$DD,B
	JMP	<STG_A
STG10	MOVE	#>10,X0		; Check for gain = x10
	CMP	X0,A
	JNE	<ERR_SGN
	MOVE	#>$EE,B

STG_A	MOVE	X:(R4)+,A	; Integrator Speed (0 for slow, 1 for fast)
	JCLR	#0,A1,STG_B
	BSET	#8,B1
	BSET	#9,B1
STG_B	MOVE	#$0C3C00,X0
	OR	X0,B
	MOVE	B,Y:<GAIN	; Store the GAIN value for later us

; Send this same value to 15 video processor boards whether they exist or not
	MOVE	#$100000,X0	; Increment value
	DO	#16,STG_LOOP
	MOVE	B,X:SSITX	; Transmit the SSI word
	JSR	<PAL_DLY	; Wait for SSI and PAL to be empty
	ADD	X0,B		; Increment the video processor board number
STG_LOOP
	JSR	<SER_UTL	; Return SSI to utility board communication
	JMP	<FINISH
ERR_SGN	MOVE	X:(R4)+,A
	JSR	<SER_UTL	; Return SSI to utility board communication
	JMP	<ERROR

;=============
;== SER_ANA ==
;=============
; Enable serial communication to the analog boards
SER_ANA BSET    #0,X:PBD        ; Set H0 for analog boards SSI
        MOVEP   #$0000,X:PCC    ; Software reset of SSI
        BCLR    #10,X:CRB       ; Change SSI to continuous clock for analog
        MOVEP   #$0160,X:PCC    ; Re-enable the SSI
        RTS

;=============
;== SER_UTL ==
;=============
; Enable serial communication to the utility board
SER_UTL MOVEP   #$0000,X:PCC    ; Software reset of SSI
        BSET    #10,X:CRB       ; Change SSI to gated clock for utility board
        MOVEP   #$0160,X:PCC    ; Enable the SSI
        BCLR    #0,X:PBD        ; Clear H0 for utility board SSI
        RTS

;======================
;== HIGAIN & LOWGAIN ==
;======================
; These are implemented for backward compatibility
HIGAIN  MOVE	#$000204,A
	MOVE	A,X:(R3)+
	MOVE    #'SGN',A	
	MOVE	A,X:(R3)+
	MOVE	#>2,A		; High gain is x 2
	MOVE	A,X:(R3)+
	MOVE	X:<ONE,A	; Fast integrator speed is 1
	MOVE	A,X:(R3)+
	JMP     <PRC_RCV

LOWGAIN	MOVE	#$000204,A
	MOVE	A,X:(R3)+
	MOVE    #'SGN',A	
	MOVE	A,X:(R3)+
	MOVE	#>1,A		; Low gain is x 1
	MOVE	A,X:(R3)+
	MOVE	X:<ONE,A	; Fast integrator speed is 1
	MOVE	A,X:(R3)+
	JMP     <PRC_RCV

;==============
;== WS_CNTRL ==
;==============
; Write an arbitraty control word over the SSI link to any register, any board
; Command syntax is  WRC number, number is 24-bit number to be sent to any board
WS_CNTRL			
	JSR	<SER_ANA	; Set SSI to analog board communication
	JSR	<PAL_DLY	; Wait for the number to be sent
        MOVEP	X:(R4)+,X:SSITX	; Send out the waveform
	JSR	<PAL_DLY	; Wait for SSI and PAL to be empty
	JSR	<SER_UTL	; Return SSI to utility board communication
	JMP	<FINISH

;============
;== SET_DC ==
;============
; Set the video processor boards in DC-coupled diagnostic mode or not
; Command syntax is  SDC #	# = 0 for normal operation
;				# = 1 for DC coupled diagnostic mode
SET_DC	JSR	<SER_ANA	; Set SSI to analog board communication
	MOVE	X:(R4)+,X0
	JSET	#0,X0,SDC_1
	BCLR	#10,Y:<GAIN
	BCLR	#11,Y:<GAIN
	JMP	<SDC_A
SDC_1	BSET	#10,Y:<GAIN
	BSET	#11,Y:<GAIN
SDC_A	MOVE	#$100000,X0	; Increment value
	DO	#15,SDC_LOOP
	MOVEP	Y:GAIN,X:SSITX
	JSR	<PAL_DLY	; Wait for SSI and PAL to be empty
	ADD	X0,B		; Increment the video processor board number
SDC_LOOP
	JSR	<SER_UTL	; Return SSI to utility board communication
	JMP	<FINISH

;==============
;== SET_BIAS ==
;==============
; Set a particular bias number, for setting DC bias voltages and 
; video processor offsets: SBN  #BOARD  #DAC  voltage
; Command syntax is  SBN  #video_board  #DAC_number  #voltage
;				#video_board is from 0 to 15
;				#DAC_number is from 0 to 15
;				#voltage is from 0 to 4095
SET_BIAS			; Set bias number
	JSR	<SER_ANA	; Set SSI to analog board communication
	MOVE	X:(R4)+,A	; First argument is board number, 0 to 15
	REP	#20
	LSL	A
	MOVE	A,X0
	MOVE	X:(R4)+,A	; Second argument is DAC number, 0 to 15
	REP	#14
	LSL	A
	OR	X0,A
	MOVE	X:(R4)+,B	; Third argument is 'VID' or 'CLK' string
	MOVE	#'VID',X0
	CMP	X0,B
	JNE	<CLK_DRV
	BSET	#19,A1		; Set bits to mean video processor DAC
	BSET	#18,A1
	JMP	<VID_BRD
CLK_DRV	MOVE	#'CLK',X0
	CMP	X0,B
	JNE	<ERR_SBN
VID_BRD	MOVE	A,X0
	MOVE	X:(R4)+,A	; Fourth argument is voltage value, 0 to $fff
	MOVE	#$000FFF,Y0	; Mask off just 12 bits to be sure
	AND	Y0,A
	OR	X0,A
	MOVEP	A,X:SSITX	; Write the number to the DAC
	JSR	<PAL_DLY	; Wait for the number to be sent
	JSR	<SER_UTL	; Return SSI to utility board communication
	JMP	<FINISH
ERR_SBN	MOVE	X:(R4)+,A	; Read and discard the fourth argument
	JSR	<SER_UTL	; Return SSI to utility board communication
	JMP	<ERROR

;=============
;== SET_MUX ==
;=============
; Specify the MUX value to be output on the clock driver board
; Command syntax is  SMX  #clock_driver_board #MUX1 #MUX2
; 			  #clock_driver_board from 0 to 15
;			  #DAC from 0 to 23
SET_MUX	JSR	<SER_ANA	; Set SSI to analog board communication
	MOVE	X:(R4)+,A	; Clock driver board number
	REP	#20
	LSL	A
	MOVE	#$003000,X0
	OR	X0,A
	MOVE	A,X1		; Move here for storage

; Get the first MUX number
	MOVE	X:(R4)+,A	; MUX number
	MOVE	A,B
	MOVE	#>7,X0
	AND	X0,B
	MOVE	#>$18,X0
	AND	X0,A
	JNE	<SMX_1		; Test for 0 <= MUX number <= 7
	BSET	#3,B1
	JMP	<SMX_A
SMX_1	MOVE	#>$8,X0
	CMP	X0,A		; Test for 8 <= MUX number <= 15
	JNE	<SMX_2
	BSET	#4,B1
	JMP	<SMX_A
SMX_2	MOVE	#>$10,X0
	CMP	X0,A		; Test for 16 <= MUX number <= 23
	JNE	<ERR_SMX
	BSET	#5,B1
SMX_A	OR	X1,B1		; Add prefix to MUX numbers
	MOVE	B1,Y1

; Add on the second MUX number
	MOVE	X:(R4)+,A	; Get the next MUX #
	REP	#6
	LSL	A
	MOVE	A,B
	MOVE	#$1C0,X0
	AND	X0,B
	MOVE	#>$600,X0
	AND	X0,A
	JNE	<SMX_3		; Test for 0 <= MUX number <= 7
	BSET	#9,B1
	JMP	<SMX_B
SMX_3	MOVE	#>$200,X0
	CMP	X0,A		; Test for 8 <= MUX number <= 15
	JNE	<SMX_4
	BSET	#10,B1
	JMP	<SMX_B
SMX_4	MOVE	#>$400,X0
	CMP	X0,A		; Test for 16 <= MUX number <= 23
	JNE	<ERR_SM2
	BSET	#11,B1
SMX_B	ADD	Y1,B		; Add prefix to MUX numbers

	MOVEP	B1,X:SSITX
	JSR	<PAL_DLY	; Delay for all this to happen
	JSR	<SER_UTL	; Return SSI to utility board communication
	JMP	<FINISH
ERR_SMX	MOVE	X:(R4)+,A
ERR_SM2	JSR	<SER_UTL	; Return SSI to utility board communication
	JMP	<ERROR

;===========
;== READM ==
;===========
; CFH12K SBUS interface only!
; Read memory
READM   MOVE    X:(R4),R0       ; Need the address in an address register
        MOVE    X:(R4)+,A       ; Need address also in a 24-bit register
READP   JCLR    #20,A,READX     ; Test address bit for P: memory
        MOVE    P:(R0),X0       ; Read from Program memory
        JMP     <SDATA
READX   JCLR    #21,A,READY     ; Test address bit for X: memory
        MOVE    X:(R0),X0       ; Read from X data memory
        JMP     <SDATA
READY   JCLR    #22,A,ERROR     ; Test address bit for Y: memory
        MOVE    Y:(R0),X0       ; Read from Y data memory
        JMP     <SDATA

;===========
;== SDATA ==
;===========
; CFH12K SBUS interface only!
; Send the 24 bits data in two 16 bits words, send header first
; -> 3x 24 bits words (3x16bits of actual information)
; Reason: 8 higner bits of the 24 bits word eaten by CFH12K interface
SDATA   MOVE    X:<HDR,A     	; Get header of incoming command
        MOVE    X:<SMASK,Y0     ; This was the source byte, and is to
        AND     Y0,A X:<THREE,Y0 ; become the destination byte
        REP     #8              ; Shift right one byte, add it to the
        LSR     A  Y0,X:<NWORDS ; header, and put 3 as the number
        ADD     Y0,A X:<SBRD,Y0 ; of words in the string
        ADD     Y0,A		; Add source boards ID
	MOVEP   A,Y:WRFO        ; Send it down the fiber
        ; Send the 16 bits high
        CLR     A
        MOVE    X0,A1           ; Memory data
        REP     #16             ; 16 shifts right to get the high 8
        LSR     A1		; bits of the 24 bits word
	MOVEP   A,Y:WRFO        ; Send it down the fiber
        REP     #60             ; A delay...
        NOP
        ; Send the 16 bits low
	MOVE	X0,A		; The lower 16 bits of the 24 bits word
	MOVEP   A,Y:WRFO        ; Send it down the fiber
        JMP     <PRC_RCV        ; Go get the next command

;===============================================================================
; 	Command table - make sure there are no more than 32 entries in it
;===============================================================================
	IF	DOWNLOAD 	
	ORG	X:COM_TBL,X:COM_TBL			; Download address
	ELSE			
        ORG     P:COM_TBL,P:APL_NUM*N_W_APL+APL_LEN+$200 	; EEPROM address
	ENDIF
	DC	'IDL',IDL  	; 1 Put CCD in IDLE mode - Not implemented
	DC	'STP',STP  	; 2 Exit IDLE mode
	DC	'SBV',SETBIAS 	; 3 Set DC bias supply voltages  
	DC	'RDC',RD_IRQ 	; 4 Begin CCD readout    
	DC	'CLR',CLEAR  	; 5 Fast clear the CCD   
	DC	'SGN',ST_GAIN  	; 6 Set video processor gain     
	DC	'WRC',WS_CNTRL	; 7 Write control word over SSI link
	DC	'SDC',SET_DC	; 8 Set DC coupled diagnostic mode
	DC	'SBN',SET_BIAS	; 9 Set bias number
	DC	'SMX',SET_MUX	; 10 Set clock driver MUX output
	DC	'DON',START	; 11 Nothing special
	DC      'WHO',WHO       ; 12 Send back DSP code ID

; This is is to read memory from the CFH12K interface box. Not SDSU!
	DC      'RM2',READM     ; 13 Read mem - split value in 2 16bits words

; These three are included for backward compatability
	DC	'RAD',FINISH	; 14 Do nothing
	DC	'HGN',HIGAIN  	; 15 Set video processor to x2 gain      
	DC	'LGN',LOWGAIN   ; 16 Set video processor to x1 gain   

	IF	DOWNLOAD
	ORG	Y:0,Y:0		; Download address
	ELSE
	ORG     Y:0,P:		; EEPROM address continues from P: above
	ENDIF
;===============================================================================
;			Y memory user's variable
;===============================================================================
OPTIONS	DC	0		;  0 Option bits word
NSR     DC      2048   	 	;  1 Number Serial Read, prescan + image + bias
NPR     DC      4096	     	;  2 Number Parallel Read of each readout only
NSCLR   DC      2049   		;  3 To clear serial register
NPCLR   DC      9000	    	;  4 To clear parallel register
NSBIN   DC      1       	;  5 Serial binning parameter (not used)
NPBIN   DC      1       	;  6 Parallel binning parameter (not used)
NPSKIP  DC      0               ;  7 Number of lines to skip before read
NSSKIP  DC      0               ;  8 Number of columns to skip before read
NSSKIP2 DC      2048            ;  9 Number of columns to skip after read
NSOVR   DC      40              ;  A Number of columns of overscan to read
NPOVR   DC      40              ;  B Number of lines of overscan to read
NSPRE   DC      50              ;  C Number of prescan pixels  
QUAD	DC	2		;  D Mosaic configuration for the test pattern
TNPR    DC      0               ;  E Total number of lines (npr+npovr)
GAIN	DC	0		;  F Video processor gain and integrator speed

; Other variables
TSTVAL  DC      0               ; 10 Increment test pattern current value
TSTOV	DC	10		; 11 Test pattern value for the overscan
SEED    DC      1               ; 12 Test pattern incr val
FBRDLY  DC      1 		; 13 Delay after sending data over the fiber
DELABL  DC      2000            ; 14 Delay for dithering antiblooming loop count
                                ;    4000=12Hz 2000=25Hz 1000=50Hz 500=100Hz

; DSP code ID
DET     DC      'EVE'           ; Detector Load file ID

;  Miscellaneous definitions for CCD operation
TST_DAT	DC	0		; Temporary definition for test images

;===============================================================================
; 		Definitions for Y: memory waveform tables
;===============================================================================
; Clocking tables must contain at least two lines, "DC      SDELAY" is a NOP
;===========
;== PXFERDUMP ==
;===========
; Transfer one line down towards the serial register and dump it with DG HIGH
PXFERDUMP
	DC	PXFER-PXFERDUMP-2  
	DC	CLK+PDELAY+P1H+P2H+P3L+DGH+RGH+S1LH+S1RH+S2LH+S2RH+S3L+SWLL+SWRL
	DC	CLK+PDELAY+P1L+P2H+P3L+DGH+RGH+S1LH+S1RH+S2LH+S2RH+S3L+SWLL+SWRL
	DC	CLK+PDELAY+P1L+P2H+P3H+DGH+RGH+S1LH+S1RH+S2LH+S2RH+S3L+SWLL+SWRL
	DC	CLK+PDELAY+P1L+P2L+P3H+DGH+RGH+S1LH+S1RH+S2LH+S2RH+S3L+SWLL+SWRL
	DC	CLK+PDELAY+P1H+P2L+P3H+DGH+RGH+S1LH+S1RH+S2LH+S2RH+S3L+SWLL+SWRL
	DC	CLK+NDELAY+P1H+P2L+P3L+DGH+RGH+S1LH+S1RH+S2LH+S2RH+S3L+SWLL+SWRL
	DC	CLK+NDELAY+P1H+P2L+P3L+DGL+RGH+S1LH+S1RH+S2LH+S2RH+S3L+SWLL+SWRL

;===========
;== PXFER ==
;===========
; Transfer one line down towards the serial register
PXFER	DC	DTHP1-PXFER-2  
	DC	CLK+PDELAY+P1H+P2H+P3L+DGL+RGH+S1LH+S1RH+S2LH+S2RH+S3L+SWLL+SWRL
	DC	CLK+PDELAY+P1L+P2H+P3L+DGL+RGH+S1LH+S1RH+S2LH+S2RH+S3L+SWLL+SWRL
	DC	CLK+PDELAY+P1L+P2H+P3H+DGL+RGH+S1LH+S1RH+S2LH+S2RH+S3L+SWLL+SWRL
	DC	CLK+PDELAY+P1L+P2L+P3H+DGL+RGH+S1LH+S1RH+S2LH+S2RH+S3L+SWLL+SWRL
	DC	CLK+PDELAY+P1H+P2L+P3H+DGL+RGH+S1LH+S1RH+S2LH+S2RH+S3L+SWLL+SWRL
	DC	CLK+NDELAY+P1H+P2L+P3L+DGL+RGH+S1LH+S1RH+S2LH+S2RH+S3L+SWLL+SWRL

;===========
;== DTHP1 ==
;===========
; Move electrons under P1
DTHP1   DC      DTHP2-DTHP1-2
	DC	CLK+PDELAY+P1H+P2H+P3L+DGL+RGH+S1LH+S1RH+S2LH+S2RH+S3L+SWLL+SWRL
        DC      CLK+NDELAY+P1H+P2L+P3L+DGL+RGH+S1LH+S1RH+S2LH+S2RH+S3L+SWLL+SWRL

;===========
;== DTHP2 ==
;===========
; Move electrons under P2
DTHP2   DC      INTG-DTHP2-2
        DC      CLK+PDELAY+P1H+P2H+P3L+DGL+RGH+S1LH+S1RH+S2LH+S2RH+S3L+SWLL+SWRL
        DC      CLK+NDELAY+P1L+P2H+P3L+DGL+RGH+S1LH+S1RH+S2LH+S2RH+S3L+SWLL+SWRL

;==========
;== INTG ==
;==========
; parallel clocking waveform for integration
INTG    DC      INVR-INTG-2
        DC      NDELAY
        DC      CLK+NDELAY+P1H+P2H+P3L+DGL+RGH+S1LH+S1RH+S2LH+S2RH+S3L+SWLL+SWRL

;==========
;== INVR ==
;==========
; parallel clocks in inversion
INVR    DC      SREV-INVR-2
        DC      NDELAY
        DC      CLK+NDELAY+P1L+P2L+P3L+DGL+RGH+S1LH+S1RH+S2LH+S2RH+S3L+SWLL+SWRL

;==========
;== SREV ==
;==========
; serial clocking voltages for cleaning
SREV    DC      RSTNODE-SREV-2
        DC      NDELAY
        DC      CLK+NDELAY+P1H+P2L+P3L+DGL+RGH+S1LH+S1RH+S2LH+S2RH+S3H+SWLL+SWRH

;=============
;== RSTNODE ==
;=============
; Serial clocking waveform for reseting the output amp
RSTNODE DC      SXFER-RSTNODE-2
	DC	VIDEO+NDELAY+%1110100	; Change nearly everything
; left amp
;        DC      CLK+RDELAY+P1H+P2L+P3L+DGL+RGH+S1LL+S1RH+S2LH+S2RL+S3L+SWLL+SWRL
; right amp
        DC      CLK+RDELAY+P1H+P2L+P3L+DGL+RGH+S1LH+S1RL+S2LL+S2RH+S3L+SWLL+SWRL

;===========
;== SXFER ==
;===========
; need to have at least 5 SDELAY lines here for it to work...
SXFER 	DC	VPROC-SXFER-2
; left amp
;        DC      CLK+SDELAY+P1H+P2L+P3L+DGL+RGL+S1LL+S1RH+S2LH+S2RL+S3L+SWLL+SWRL
;        DC      CLK+SDELAY+P1H+P2L+P3L+DGL+RGL+S1LL+S1RH+S2LH+S2RL+S3H+SWLH+SWRL
;        DC      CLK+SDELAY+P1H+P2L+P3L+DGL+RGL+S1LL+S1RL+S2LL+S2RL+S3H+SWLH+SWRL
;        DC      CLK+SDELAY+P1H+P2L+P3L+DGL+RGL+S1LH+S1RL+S2LL+S2RH+S3H+SWLH+SWRL
;        DC      CLK+$200000+P1H+P2L+P3L+DGL+RGL+S1LH+S1RL+S2LL+S2RH+S3L+SWLH+SWRL
; right amp
        DC      CLK+SDELAY+P1H+P2L+P3L+DGL+RGL+S1LH+S1RL+S2LL+S2RH+S3L+SWLL+SWRL
        DC      CLK+SDELAY+P1H+P2L+P3L+DGL+RGL+S1LH+S1RL+S2LL+S2RH+S3H+SWLL+SWRH
        DC      CLK+SDELAY+P1H+P2L+P3L+DGL+RGL+S1LL+S1RL+S2LL+S2RL+S3H+SWLL+SWRH
        DC      CLK+SDELAY+P1H+P2L+P3L+DGL+RGL+S1LL+S1RH+S2LH+S2RL+S3H+SWLL+SWRH
        DC      CLK+$200000+P1H+P2L+P3L+DGL+RGL+S1LL+S1RH+S2LH+S2RL+S3L+SWLL+SWRH


;===========
;== VPROC ==
;===========
; A/D, integ, Pol+, Pol-, DCrestore, rst   (1 => switch open)
VPROC   DC      SSKIP-VPROC-2
; left amp
;        DC    	SXMIT                  ; Transmit A/D data to host
;        DC      VIDEO+NDELAY+%1110111  ; Stop resetting integrator
;        DC      VIDEO+NDELAY+%1110111  ; Stop resetting integrator
;        DC      VIDEO+VDELAY+%0000111  ; Integrate for 1 microsec
;        DC      VIDEO+NDELAY+%0011011  ; Stop Integrate
;        DC      CLK+$200000+P1H+P2L+P3L+DGL+RGL+S1LH+S1RL+S2LL+S2RH+S3L+SWLL+SWRL
;        DC      VIDEO+NDELAY+%1110111  ; Stop resetting integrator
;        DC      VIDEO+NDELAY+%0011011  ; Delay for signal to settle
;        DC      VIDEO+VDELAY+%0001011  ; Integrate for another microsec
;        DC      VIDEO+NDELAY+%0011011  ; Stop integrate, A/D is sampling
;        DC      CLK+SDELAY+P1H+P2L+P3L+DGL+RGL+S1LH+S1RH+S2LH+S2RH+S3L+SWLL+SWRL
; right amp
        DC    	SXMIT                  ; Transmit A/D data to host
        DC      VIDEO+NDELAY+%1110111  ; Stop resetting integrator
        DC      VIDEO+NDELAY+%1110111  ; Stop resetting integrator
        DC      VIDEO+VDELAY+%0000111  ; Integrate for 1 microsec
        DC      VIDEO+NDELAY+%0011011  ; Stop Integrate
        DC      CLK+$200000+P1H+P2L+P3L+DGL+RGL+S1LL+S1RH+S2LH+S2RL+S3L+SWLL+SWRL
        DC      VIDEO+NDELAY+%1110111  ; Stop resetting integrator
        DC      VIDEO+NDELAY+%0011011  ; Delay for signal to settle
        DC      VIDEO+VDELAY+%0001011  ; Integrate for another microsec
        DC      VIDEO+NDELAY+%0011011  ; Stop integrate, A/D is sampling
        DC      CLK+SDELAY+P1H+P2L+P3L+DGL+RGL+S1LH+S1RH+S2LH+S2RH+S3L+SWLL+SWRL


;===========
;== SSKIP ==
;===========
; Serial clocking waveform for skipping
SSKIP   DC	DACS-SSKIP-2
; right amp
        DC      CLK+RDELAY+P1H+P2L+P3L+DGL+RGH+S1LH+S1RL+S2LL+S2RH+S3L+SWLL+SWRL
        DC      CLK+NDELAY+P1H+P2L+P3L+DGL+RGL+S1LH+S1RL+S2LL+S2RH+S3L+SWLL+SWRL
        DC      CLK+NDELAY+P1H+P2L+P3L+DGL+RGL+S1LH+S1RL+S2LL+S2RH+S3H+SWLL+SWRH
        DC      CLK+NDELAY+P1H+P2L+P3L+DGL+RGL+S1LL+S1RL+S2LL+S2RL+S3H+SWLL+SWRH
        DC      CLK+NDELAY+P1H+P2L+P3L+DGL+RGL+S1LL+S1RH+S2LH+S2RL+S3H+SWLL+SWRH
        DC      CLK+NDELAY+P1H+P2L+P3L+DGL+RGL+S1LL+S1RH+S2LH+S2RL+S3L+SWLL+SWRH
        DC      CLK+NDELAY+P1H+P2L+P3L+DGL+RGL+S1LL+S1RH+S2LH+S2RL+S3L+SWLL+SWRL
        DC      CLK+NDELAY+P1H+P2L+P3L+DGL+RGL+S1LH+S1RH+S2LH+S2RH+S3L+SWLL+SWRL


;==========
;== DACS ==
;==========
; Initialization of clock driver and video processor DACs and switches
DACS	DC	END_DACS-DACS-1
        ; DAC Clocking Boards 1 ->{CCD1,CCD2}  CCD A & CCD B
        ; Device A
        DC      (DAC1<<8)+(00<<14)+R_HI ; pin  1 - CCD A - RG High
        DC      (DAC1<<8)+(01<<14)+R_LO ; 	   CCD A - RG Low
        DC      (DAC1<<8)+(02<<14)+S_HI ; pin  2 - CCD A - S1L High
        DC      (DAC1<<8)+(03<<14)+S_LO ; 	   CCD A - S1L Low
        DC      (DAC1<<8)+(04<<14)+S_HI ; pin  3 - CCD A - S1R High
        DC      (DAC1<<8)+(05<<14)+S_LO ; 	   CCD A - S1R Low
        DC      (DAC1<<8)+(06<<14)+S_HI ; pin  4 - CCD A - S2L High
        DC      (DAC1<<8)+(07<<14)+S_LO ; 	   CCD A - S2L Low
        DC      (DAC1<<8)+(08<<14)+S_HI ; pin  5 - CCD A - S2R High
        DC      (DAC1<<8)+(09<<14)+S_LO ; 	   CCD A - S2R Low
        DC      (DAC1<<8)+(10<<14)+S_HI ; pin  6 - CCD A - S3 High
        DC      (DAC1<<8)+(11<<14)+S_LO ; 	   CCD A - S3 Low
        DC      (DAC1<<8)+(12<<14)+W_HI ; pin  7 - CCD A - SWL High
        DC      (DAC1<<8)+(13<<14)+W_LO ; 	   CCD A - SWL Low
        DC      (DAC1<<8)+(14<<14)+W_HI ; pin  8 - CCD A - SWR High
        DC      (DAC1<<8)+(15<<14)+W_LO ; 	   CCD A - SWR Low 
        DC      (DAC1<<8)+(16<<14)+P_HI ; pin  9 - CCD A - P1 High 
        DC      (DAC1<<8)+(17<<14)+P_LO ; 	   CCD A - P1 Low 
        DC      (DAC1<<8)+(18<<14)+P_HI ; pin 10 - CCD A - P2 High
        DC      (DAC1<<8)+(19<<14)+P_LO ; 	   CCD A - P2 Low
        DC      (DAC1<<8)+(20<<14)+P_HI ; pin 11 - CCD A - P3 High
        DC      (DAC1<<8)+(21<<14)+P_LO ; 	   CCD A - P3 Low 
        DC      (DAC1<<8)+(22<<14)+R_HI+$200 ; pin 12 - CCD A - DG High
        DC      (DAC1<<8)+(23<<14)+R_LO ; 	   CCD A - DG Low
        ; Device B
        DC      (DAC1<<8)+(24<<14)+R_HI ; pin 13 - CCD B - RG High
        DC      (DAC1<<8)+(25<<14)+R_LO ;          CCD B - RG Low
        DC      (DAC1<<8)+(26<<14)+S_HI ; pin 14 - CCD B - S1 High
        DC      (DAC1<<8)+(27<<14)+S_LO ;          CCD B - S1 Low
        DC      (DAC1<<8)+(28<<14)+S_HI ; pin 15 - CCD B - S2 High
        DC      (DAC1<<8)+(29<<14)+S_LO ;          CCD B - S2 Low
        DC      (DAC1<<8)+(30<<14)+S_HI ; pin 16 - CCD B - S3 High
        DC      (DAC1<<8)+(31<<14)+S_LO ;          CCD B - S3 Low
        DC      (DAC1<<8)+(32<<14)+P_HI ; pin 17 - CCD B - P1 High BOTTOM
        DC      (DAC1<<8)+(33<<14)+P_LO ;          CCD B - P1 Low  BOTTOM
        DC      (DAC1<<8)+(34<<14)+P_HI ; pin 18 - CCD B - P2 High BOTTOM
        DC      (DAC1<<8)+(35<<14)+P_LO ;          CCD B - P2 Low  BOTTOM
        DC      (DAC1<<8)+(36<<14)+P_HI ; pin 19 - CCD B - P3 High BOTTOM
        DC      (DAC1<<8)+(37<<14)+P_LO ;          CCD B - P3 Low  BOTTOM
        DC      (DAC1<<8)+(38<<14)+W_HI ; pin 33 - CCD B - SW High LEFT
        DC      (DAC1<<8)+(39<<14)+W_LO ;          CCD B - SW Low  LEFT
        DC      (DAC1<<8)+(40<<14)+W_HI ; pin 34 - CCD B - SW High RIGHT
        DC      (DAC1<<8)+(41<<14)+W_LO ;          CCD B - SW Low  RIGHT
        DC      (DAC1<<8)+(42<<14)+P_HI ; pin 35 - CCD B - P1 High TOP
        DC      (DAC1<<8)+(43<<14)+P_LO ;          CCD B - P1 Low  TOP
        DC      (DAC1<<8)+(44<<14)+P_HI ; pin 36 - CCD B - P2 High TOP
        DC      (DAC1<<8)+(45<<14)+P_LO ;          CCD B - P2 Low  TOP
        DC      (DAC1<<8)+(46<<14)+P_HI ; pin 37 - CCD B - P3 High TOP
        DC      (DAC1<<8)+(47<<14)+P_LO ;          CCD B - P3 Low  TOP

 
 
; Set gain and integrator speed. x 9.5 gain, fast integrate - All boards
; For fullframe fast readout at 2D integration times
;	DC	(BIAS1<<8)+GAININT+$FEE	; Gain, integrate speed, board #1 fast x 10
; this one gives about the same gain as the Gecko setting
;	DC	(BIAS1<<8)+GAININT+$FDD	; Gain, integrate speed, board #1 fast x 4.75
;	DC	(BIAS1<<8)+GAININT+$C77	; Gain, integrate speed, board #1 slow x 1
; For Gecko with B8 as integration times
	DC	(BIAS1<<8)+GAININT+$CBB	; Gain, integrate speed, board #1 slow x 2

; Input offset voltages for DC coupling - All boards - Target U4#6=24 volts
	DC	(BIAS1<<8)+INOFFA+$800	; Input offset, CCD A  board #1
	DC	(BIAS1<<8)+INOFFB+$800	; Input offset, CCD B  board #1

; Output offset voltages to get offset on bias frame - All boards
        DC      (BIAS1<<8)+OUTOFFA+$700 ; Output offset, CCD A, board #1
        DC      (BIAS1<<8)+OUTOFFB+$840 ; Output offset, CCD B, board #1 ~500 ADU

; DC bias voltages: VOD, VRD, VOG
        ; Amplifier voltages - First board {CCD1,CCD2}
        ; LEFT AMP
	DC      (BIAS1<<8)+VODL+$AAA	; VODL =  ???V - CCD A, board #1 B3E best
        DC      (BIAS1<<8)+VRDL+$5FE    ; VRDL = ??? V - CCD A, board #1 806 best
        DC      (BIAS1<<8)+VDD+$C30     ; VDD = 16.0 V - CCD A, board #1 C30
        DC      (BIAS1<<8)+VOG1+$185    ; VOG1 = -4.0 V - CCD A, board #1
        ; RIGHT AMP
	DC      (BIAS1<<8)+VODR+$AAA	; VODR =  22.5V - CCD B, board #1 ???
        DC      (BIAS1<<8)+VRDR+$5FE    ; VRDR =  10.62V - CCD B, board #1 ???
        DC      (BIAS1<<8)+VOG2+$380    ; VOG2 = -3.0 V - CCD B, board #1

END_DACS

;===============================================================================
; Check for overflow in the EEPROM case
	IF !DOWNLOAD
		IF	@CVS(N,@LCV(L))>(APL_NUM+1)*N_W_APL
	WARN    'EEPROM overflow!'	; Make sure next application
		ENDIF			;  will not be overwritten
	ENDIF
;===============================================================================
	ENDSEC		; End of section EEV1E
;  End of program
	END