COMMENT *

This file is used to generate DSP code for the TIMII second generation 
    timing board. This is Rev. 3.00 software.     

Timing modified for Datel A/D converter starting 11-6-96
Modified for timing board Rev. 4B Feb. 17, 1997
Rarely used and non-time critical code are in SRAM program memory (P: > $200)

-d DOWNLOAD 1	To generate code for downloading to DSP memory.
-d DOWNLOAD 0	To generate code for writing to the EEPROM.

;  ph mods to setup different wipe
	comments to next line
	*	
	PAGE    132     ; Printronix page width - 132 columns

; Define a section name so it doesn't conflict with other application programs
	SECTION	TIM

; These are also defined in "timboot.asm", so be sure they agree
APL_NUM	EQU	1	; Application number from 1 to 10
APL_ADR	EQU	$100	; P: memory location where application code begins
APL_LEN	EQU	$200-APL_ADR ; Maximum length of application program
COM_TBL EQU     $80     ; Starting address of command table in X: memory

; Board status bits, defined at X:<STATUS = X:0
IDLING  EQU     0	; Set if in idle mode => clocking out
IDLMODE	EQU	1	; Set if need to idle after readout
ST_RDC	EQU	4	; Set if executing 'RDC' command - reading out

; Define some timing board addresses
WRLATCH	EQU	$FFC1	; Write to timing board latch
WRFO	EQU	$FFC0	; Write to fiber optic transmitter
RDAD0	EQU	$FFA0	; Address for reading A/D #0
RDAD1	EQU	$FFA1	; Address for reading A/D #1
SSITX	EQU	$FFEF	; SSI Transmit and Receive data register
SSISR	EQU	$FFEE	; SSI Status Register
PBD	EQU	$FFE4	; Port B Data Register
PCC     EQU     $FFE1   ; Port C Control Register
PCDDR	EQU	$FFE3	; Port C Data Direction Register
PCD     EQU     $FFE5   ; Port C Data Register
BCR     EQU     $FFFE   ; Bus (=Port A) Control Register -> Wait States
RSTWDT	EQU	$6000	; Address to reset the timing board watchdog timer

; CCD clock voltage definitions
VIDEO	EQU	$000000	; Video processor board select = 0
BD2	EQU	$002000	; Clock driver board select = 2 
BD3	EQU	$003000	; Clock driver board select = 3 
P_DELAY	EQU	$ff0000	; Maximum delay for parallels = 25 microsec
S_DELAY	EQU	$500000	; Test serial delay
R_HI	EQU	3000	; Reset and Serial clocks High +4.0 volts
R_LO	EQU	770	; Reset and Serial clocks Low  -6.0 volts
SI_HI	EQU	2710	; Storage and Image High +3.0 volts
SI_LO	EQU	620	; Storage and Image Low  -7.0 volts
WW	EQU	1	; Word width = 1 for 16-bit image data, 0 for 24-bit
LVEN	EQU     2       ; Low voltage PS enable (+/-15 volt nominal)
HVEN	EQU     3       ; Enable high voltage PS (+32V nominal)- Output
PWRST	EQU     13      ; Power control board reset
SYNC	EQU	11	; Master/Slave synchronization bit
CDAC	EQU	0	; Bit number in U25 for clearing DACs
ENCK	EQU	2	; Bit number in U25 for enabling analog switches

;SXMIT	EQU     $00F060	; Series transmit A/D channels #0 to #3
;SXMIT	EQU     $00F020	; Series transmit A/D channels #0 to #1
;SXMIT	EQU     $00F000	; Series transmit A/D channel #0 only
;SXMIT  EQU     $00F021	; Series transmit A/D channel #1 only
;SXMIT  EQU     $00F042	; Series transmit A/D channel #2 only
;SXMIT  EQU     $00F063	; Series transmit A/D channel #3 only
;SXMIT  EQU     $00F062	; Series transmit A/D channels #2 to #3

; Single readout of the B amplifier
SXMIT	EQU     $00F021

;**************************************************************************
;                   	                                                  *
;    Permanent address register assignments                               *
;	 R1 - Address of SSI receiver contents				  *
;	 R2 - Address of SCI receiver contents				  *
;        R3 - Pointer to current top of command buffer                    *
;        R4 - Pointer to processed contents of command buffer		  *
;        R5 - Temporary register for processing SSI and SCI contents      *
;        R6 - CCD clock driver address for CCD #0 = $FF80                 *
;                It is also the A/D address of analog board #0            *
;                                                                         *
;    Other registers                                                      *
;        R0, R7 - Temporary registers used all over the place.            *
;        R5 - Can be used as a temporary register but is circular,        *
;               modulo 32.       					  *
;**************************************************************************

;  Specify execution and load addresses
	IF	DOWNLOAD
	ORG	P:APL_ADR,P:APL_ADR		; Download address
	ELSE
	ORG     P:APL_ADR,P:(2*APL_NUM-1)*$100	; EEPROM generation
	ENDIF

; Keep the CCD idling when not reading out
IDLE	DO      Y:<NSR,IDL1     ; Loop over number of pixels per line
;	MOVE    #<SERIAL_IDLE,R0 ; Serial transfer on pixel
;	JSR     <CLOCK  	; Go to it
	JSR	<GET_RCV	; Check for FO or SSI commands
	JCC	<NO_COM		; Continue IDLE if no commands received
	MOVE    #<SERIAL_IDLE,R0 ; Serial transfer on pixel
	JSR     <CLOCK  	; Go to it
	ENDDO   		; Cancel the DO loop system stack numbers
	JMP     <CHK_SSI	; Go process header and command
NO_COM  NOP
IDL1	
	MOVE    #<PARALLEL,R0	; move address of parallel clocking waveform
				; to R0 for slow_clock to use
;	JSR     <SLOW_CLOCK  	; Go clock out the CCD charge
	JSR     <FLUSH_CLOCK  	; Go clock out the CCD charge
	JMP     <IDLE

; Set software to IDLE mode
IDL	BSET    #IDLING,X:<STATUS
	JMP     <FINISH		; Need to send header ID and 'DON'

; Come to here on a 'STP' command so 'DON' can be sent
STP     BCLR    #IDLING,X:<STATUS
	JMP     <FINISH

; Fast clear (flush) image before each exposure
CLEAR	DO      Y:<NPCLR,LPCLR	; Loop over number of lines in image
	NOP
	MOVE    #<PARA_FLUSH,R0	; Address of parallel transfer waveform
                        	; with all serials +ve
	JSR     <FLUSH_CLOCK  	; Go clock out the CCD charge
	NOP			; Do loop restriction
LPCLR
	BCLR	#IDLMODE,X:<STATUS
	JCLR	#IDLING,X:<STATUS,FINISH
	BSET	#IDLMODE,X:<STATUS	; Idle after readout
	BCLR    #IDLING,X:<STATUS 	; Don't idle during exposure
	JMP     <FINISH

; Set all the DC bias voltages and video processor offset values, reading
;   them from the table labeled DACS in this file
SETBIAS	JSR	<SER_ANA
	BSET	#CDAC,X:<LATCH	; Disable clearing of DACs
	BSET	#ENCK,X:<LATCH	; Enable clock and DAC output switches
	MOVEP	X:LATCH,Y:WRLATCH ; Disable clearing of DAC and enable clocks
	JSR	<PAL_DLY	; Delay for all this to happen
	JSR	<PAL_DLY	; Delay for all this to happen

; Read DAC values from a table, and set DACs
	MOVE	#DACS,R0	; Get starting address of DAC values
	JSR	<SET_DAC

; Set all video processor analog switches to open to disable them (1 => OFF)
	MOVE	#$000FFF,A 
	MOVE    A,X:(R6)	; Send out the waveform
	NOP

; Let the DAC voltages all ramp up before exiting
	MOVE	#400,A		; Delay 4 millisec
	DO	A,L_SBV1
	JSR	<PAL_DLY 	; Delay for all this to happen
	NOP
L_SBV1
	JSR	<SER_UTL	; Return SSI to utility board communication
	JMP	<FINISH

; Enable serial communication to the analog boards
SER_ANA	BSET	#0,X:PBD	; Set H0 for analog boards SSI
	MOVEP	#$0000,X:PCC	; Software reset of SSI
	BCLR	#10,X:CRB	; Change SSI to continuous clock for analog 
	MOVEP   #$0160,X:PCC	; Re-enable the SSI
	RTS

; Enable serial communication to the utility board
SER_UTL	MOVEP	#$0000,X:PCC	; Software reset of SSI
	BSET	#10,X:CRB	; Change SSI to gated clock for utility board 
	MOVEP   #$0160,X:PCC	; Enable the SSI
	BCLR	#0,X:PBD	; Clear H0 for utility board SSI
	RTS

; Abort readout
ABORT	NOP			; Aborting readout not yet implemented	
CONT_RD	NOP

;  ***********************   CCD  READOUT   ***********************
; Overall loop - transfer and read NPR lines
;
; Clear out the serial shift register
RDCCD	BSET	#ST_RDC,X:<STATUS ; Set status to reading out
	BSET	#1,X:PBD	; Set WW = 1 for 16-bit image data
	MOVE	#(END_SERIAL-SERIAL-1),M1
	MOVE	#(END_SERIAL-SERIAL),X0
	MOVE	Y:<NSR,X1	; Compute number of waveform entries
	MPY	X0,X1,B         ; nsr * num waveforms 
	ASR	B		; Correct for multiplication left shift
; This line needs to be commented out if you are doing single readout.
; For dual readout remove the semi-colon
;	ASR	B		; /2 for dual or quad readout
	MOVE	B0,A
	MOVE	X:<ONE,X1
	SUB	X1,A
	MOVE	A,X1		; X1 = (END_SERIAL-SERIAL) * NSR - 1
	CLR	A

	DO      Y:<NSCLR,LSCLR	; Loop over number of pixels to skip
        MOVE    #<SSKIP,R0      ; Address of serial skipping waveforms
;        JSR     <CLOCK          ; Go clock out the CCD charge
        JSR     <SLOW_CLOCK          ; Go clock out the CCD charge
        NOP                     ; Do loop restriction
LSCLR  

; Start the loop for parallel shifting desired number of lines
	DO      Y:<NPR,LPR      ; Loop over each line readout
	MOVE	A,P:RSTWDT 	; Reset watchdog timer

; High efficiency serial shift code
DEBUG	MOVE	#<SERIAL,R1
	MOVE    #<PARALLEL,R0	; Address of parallel clocking waveform
	JSR     <SLOW_CLOCK     ; Go clock out 1 line of the CCD charge
        MOVE    Y:(R1)+,A       ; Start the pipeline
	DO	X1,LSR		; Number of waveform entries per line
        MOVE    A,X:(R6) Y:(R1)+,A      ; Send out the waveform
LSR
        MOVE    A,X:(R6)        ; Flush out the pipeline
LPR				; End of loop label for parallel register

;	JMP	<DEBUG		; Uncomment for continuous scoping

	BCLR	#1,X:PBD	; Clear WW to 0 for 32-bit commands
	BCLR	#ST_RDC,X:<STATUS ; Set status to reading out
	JCLR	#IDLMODE,X:<STATUS,START ; Don't idle after readout
	BSET	#IDLING,X:<STATUS ; Idle after readout
        JMP     <START		; Wait for a new command

;  *************************    SUBROUTINES    ***********************
; Delay for serial writes to the PALs and DACs by 8 microsec
PAL_DLY	DO	#250,DLY	 ; Wait 8 usec for serial data transmission
	NOP
	NOP
DLY	NOP
	RTS

;  Update the DACs
SET_DAC	MOVE	Y:(R0)+,X0		; Get the number of table entries
        DO      X0,SET_L0		; Repeat X0 times
        MOVEP	Y:(R0)+,X:SSITX		; Send out the waveform
	JSR	<PAL_DLY		; Wait for SSI and PAL to be empty
	NOP				; Do loop restriction
SET_L0
        RTS                     	; Return from subroutine

; Core subroutine for clocking out CCD charge
; original SDSU routine
CLOCK   MOVE    Y:(R0)+,X0      ; # of waveform entries 
        MOVE    Y:(R0)+,A       ; Start the pipeline
        DO      X0,CLK1                 ; Repeat X0 times
        MOVE    A,X:(R6) Y:(R0)+,A      ; Send out the waveform
CLK1
        MOVE    A,X:(R6)        ; Flush out the pipeline
        RTS                     ; Return from subroutine

; Clocking subroutine for very long parallel clocks for site 4096k
; use this one to read the chip out slowly to maintain full well
SLOW_CLOCK
	MOVE	Y:(R0)+,A	; move Number of waveform entries to accum
				; and increment Y:address 
	MOVE	X:<ONE,X0
	ADD	X0,A		; 
	DO	A,L_CLK	
	MOVE	Y:(R0)+,A	; Get the waveform
	DO	Y:<N_PAR,L_LOOP	; lengthen it by Loop over it N_PAR times
	MOVE	A,X:(R6)	; Write it to the hardware
L_LOOP
	NOP
L_CLK
	RTS

; Clocking subroutine for long parallel clocks for site 4096k
; use this one to read flush and idle the ccd
FLUSH_CLOCK
	MOVE	Y:(R0)+,A	; Number of waveform entries
	MOVE	X:<ONE,X0
	ADD	X0,A
	DO	A,FL_CLK	
	MOVE	Y:(R0)+,A	; Get the waveform
	DO	Y:<N_FPAR,FL_LOOP ;lengthen it by Loop over it N_FPAR times
	MOVE	A,X:(R6)	; Write it to the hardware
FL_LOOP
	NOP
FL_CLK
	RTS

; Check for program overflow
        IF	@CVS(N,*)>=$200
        WARN    'Application P: program is too large!'	; Make sure program
	ENDIF						;  will not overflow

;  ****************  PROGRAM CODE IN SRAM PROGRAM SPACE    *******************
; Put all the following code in SRAM, starting at P:$200. Load Application is
;   not yet supported
	ORG	P:$200,P:$200	; Download address

; Set the video processor gain and integrator speed for all video boards
;  Command syntax is  SGN  #GAIN  #SPEED, #GAIN = 1, 2, 5 or 10	
;					  #SPEED = 0 for slow, 1 for fast
ST_GAIN	JSR	<SER_ANA	; Set SSI to analog board communication
	MOVE	X:(R4)+,A	; Gain value (1,2,5 or 10)
	MOVE	#>1,X0
	CMP	X0,A		; Check for gain = x1
	JNE	<STG2
	MOVE	#>$77,B
	JMP	<STG_A
STG2	MOVE	#>2,X0		; Check for gain = x2
	CMP	X0,A
	JNE	<STG5
	MOVE	#>$BB,B
	JMP	<STG_A
STG5	MOVE	#>5,X0		; Check for gain = x5
	CMP	X0,A
	JNE	<STG10
	MOVE	#>$DD,B
	JMP	<STG_A
STG10	MOVE	#>10,X0		; Check for gain = x10
	CMP	X0,A
	JNE	<ERROR
	MOVE	#>$EE,B

STG_A	MOVE	X:(R4)+,A	; Integrator Speed (0 for slow, 1 for fast)
	JCLR	#0,A1,STG_B
	BSET	#8,B1
	BSET	#9,B1
STG_B	MOVE	#$0C3C00,X0
	OR	X0,B
	MOVE	B,Y:<GAIN	; Store the GAIN value for later us

; Send this same value to 15 video processor boards whether they exist or not
	MOVE	#$100000,X0	; Increment value
	DO	#15,STG_LOOP
	MOVE	B,X:SSITX	; Transmit the SSI word
	JSR	<PAL_DLY	; Wait for SSI and PAL to be empty
	ADD	X0,B		; Increment the video processor board number
STG_LOOP

	JSR	<SER_UTL	; Return SSI to utility board communication
	JMP	<FINISH

; These are implemented for backward compatibility
HIGAIN  MOVE	#$000204,A
	MOVE	A,X:(R3)+
	MOVE    #'SGN',A	
	MOVE	A,X:(R3)+
	MOVE	#>2,A		; High gain is x 2
	MOVE	A,X:(R3)+
	MOVE	X:<ONE,A	; Fast integrator speed is 1
	MOVE	A,X:(R3)+
	JMP     <PRC_RCV

LOWGAIN	MOVE	#$000204,A
	MOVE	A,X:(R3)+
	MOVE    #'SGN',A	
	MOVE	A,X:(R3)+
	MOVE	#>1,A		; Low gain is x 1
	MOVE	A,X:(R3)+
	MOVE	X:<ONE,A	; Fast integrator speed is 1
	MOVE	A,X:(R3)+
	JMP     <PRC_RCV

; Write an arbitraty control word over the SSI link to any register, any board
; Command syntax is  WRC number, number is 24-bit number to be sent to any board
WR_CNTRL			
	JSR	<SER_ANA	; Set SSI to analog board communication
	JSR	<PAL_DLY	; Wait for the number to be sent
        MOVEP	X:(R4)+,X:SSITX	; Send out the waveform
	JSR	<PAL_DLY	; Wait for SSI and PAL to be empty
	JSR	<SER_UTL	; Return SSI to utility board communication
	JMP	<FINISH

; Set the video processor boards in DC-coupled diagnostic mode or not
; Command syntax is  SDC #	# = 0 for normal operation
;				# = 1 for DC coupled diagnostic mode
SET_DC	JSR	<SER_ANA	; Set SSI to analog board communication
	MOVE	X:(R4)+,X0
	JSET	#0,X0,SDC_1
	BCLR	#10,Y:<GAIN
	BCLR	#11,Y:<GAIN
	JMP	<SDC_A
SDC_1	BSET	#10,Y:<GAIN
	BSET	#11,Y:<GAIN
SDC_A	MOVE	#$100000,X0	; Increment value
	DO	#15,SDC_LOOP
	MOVEP	Y:GAIN,X:SSITX
	JSR	<PAL_DLY	; Wait for SSI and PAL to be empty
	ADD	X0,B		; Increment the video processor board number
SDC_LOOP
	JSR	<SER_UTL	; Return SSI to utility board communication
	JMP	<FINISH

; Set a particular bias number, for setting DC bias voltages and 
;   video processor offsets: SBN  #BOARD  #DAC  voltage
; Command syntax is  SBN  #video_board  #DAC_number  #voltage
;				#video_board is from 0 to 15
;				#DAC_number is from 0 to 15
;				#voltage is from 0 to 4095
SET_BIAS_NUMBER			; Set bias number
	JSR	<SER_ANA	; Set SSI to analog board communication
	MOVE	X:(R4)+,A	; First argument is board number, 0 to 15
	REP	#20
	LSL	A
	MOVE	A,X0
	MOVE	X:(R4)+,A	; Second argument is DAC number, 0 to 15
	REP	#14
	LSL	A
	OR	X0,A
	BSET	#19,A1		; Set bits meaning DAC
	BSET	#18,A1
	MOVE	A,X0
	MOVE	X:(R4)+,A	; Third argument is voltage value, 0 to $fff
	MOVE	#$000FFF,Y0	; Mask off just 12 bits to be sure
	AND	Y0,A
	OR	X0,A
	MOVEP	A,X:SSITX	; Write the number to the DAC
	JSR	<PAL_DLY	; Wait for the number to be sent
	JSR	<SER_UTL	; Return SSI to utility board communication
	JMP	<FINISH

; Specify the MUX value to be output on the clock driver board
; Command syntax is  SMX  #clock_driver_board #MUX1 #MUX2
;				#clock_driver_board from 0 to 15
;				#DAC from 0 to 23
SET_MUX	JSR	<SER_ANA	; Set SSI to analog board communication
	MOVE	X:(R4)+,A	; Clock driver board number
	REP	#20
	LSL	A
	MOVE	#$003000,X0
	OR	X0,A
	MOVE	A,X1		; Move here for storage

; Get the first MUX number
	MOVE	X:(R4)+,A	; MUX number
	MOVE	A,B
	MOVE	#>7,X0
	AND	X0,B
	MOVE	#>$18,X0
	AND	X0,A
	JNE	<SMX_1		; Test for 0 <= MUX number <= 7
	BSET	#3,B1
	JMP	<SMX_A
SMX_1	MOVE	#>$10,X0
	CMP	X0,A		; Test for 8 <= MUX number <= 15
	JNE	<SMX_2
	BSET	#4,B1
	JMP	<SMX_A
SMX_2	MOVE	#>$20,X0
	CMP	X0,A		; Test for 16 <= MUX number <= 23
	JNE	<ERROR
	BSET	#5,B1
SMX_A	OR	X1,B1		; Add prefix to MUX numbers
	MOVE	B1,Y1

; Add on the second MUX number
	MOVE	X:(R4)+,A	; For the next MUX #
	REP	#6
	LSL	A
	MOVE	A,B
	MOVE	#$1C0,X0
	AND	X0,B
	MOVE	#>$600,X0
	AND	X0,A
	JNE	<SMX_3		; Test for 0 <= MUX number <= 7
	BSET	#10,B1
	JMP	<SMX_A
SMX_3	MOVE	#>$200,X0
	CMP	X0,A		; Test for 8 <= MUX number <= 15
	JNE	<SMX_4
	BSET	#11,B1
	JMP	<SMX_B
SMX_4	MOVE	#>$400,X0
	CMP	X0,A		; Test for 16 <= MUX number <= 23
	JNE	<ERROR
	BSET	#12,B1
SMX_B	ADD	Y1,B		; Add prefix to MUX numbers

	MOVEP	B1,X:SSITX
	JSR	<PAL_DLY	; Delay for all this to happen
	JSR	<SER_UTL	; Return SSI to utility board communication
	JMP	<FINISH

; ***********  DATA AREAS - READOUT PARAMETERS AND WAVEFORMS  ************

; Command table
	IF	DOWNLOAD 	; Memory offsets for downloading code
	ORG	X:COM_TBL,X:COM_TBL
	ELSE			; Memory offsets for generating EEPROMs
        ORG     P:COM_TBL,P:(2*APL_NUM-1)*$100+APL_LEN
	ENDIF
	DC	'IDL',IDL  	; Put CCD in IDLE mode    
	DC	'STP',STP  	; Exit IDLE mode
	DC	'SBV',SETBIAS 	; Set DC bias supply voltages  
	DC	'RDC',RDCCD 	; Begin CCD readout    
	DC	'CLR',CLEAR  	; Fast clear the CCD   
	DC	'SGN',ST_GAIN  	; Set video processor gain     
	DC	'WRC',WR_CNTRL	; Write control word over SSI link
	DC	'SDC',SET_DC	; Set DC coupled diagnostic mode
	DC	'SBN',SET_BIAS_NUMBER	; Set bias number
	DC	'SMX',SET_MUX	; Set clock driver MUX output
	DC	'ABR',ABORT	; Abort exposure readout
	DC	'CRD',CONT_RD	; Continue reading out
	DC	'DON',START	; Nothing special

; These three are included for backward compatability
	DC	'RAD',FINISH	; Do nothing
	DC	'HGN',HIGAIN  	; Set video processor to x2 gain      
	DC	'LGN',LOWGAIN   ; Set video processor to x1 gain   

	IF	DOWNLOAD
	ORG	Y:0,Y:0		; Download address
	ELSE
	ORG     Y:0,P:		; EEPROM address continues from P: above
	ENDIF
GAIN	DC	0		; Video processor gain and integrator speed
NSR     DC      2150   	 	; Number Serial Read, prescan + image + bias
NPR     DC      4150	     	; Number Parallel Read of each readout only
NSCLR   DC      5000    	; To clear serial register

; npclr originally 4 times 4096 || clocks with no N_PAR
; then 1000 || clocks with 50 N_PAR, cleared ok on controller reset
;NPCLR   DC      16284	    	; To clear parallel register 

NPCLR   DC      5000	    	; To clear parallel register
NSBIN   DC      1       	; Serial binning parameter (not used)
NPBIN   DC      1       	; Parallel binning parameter (not used)
N_PAR	DC	50		; Number of times each waveform is sent out
N_FPAR  DC 	10              ;  


; Miscellaneous definitions for CCD operation
TST_DAT	DC	0		; Temporary definition for test images

; Define switch state bits for the CCD clocks of the SITe
RGA_L	EQU	0
RGA_H	EQU	1	; Pin #1, Reset Gate, side A, clock driver board #0
RGB_L	EQU	0	
RGB_H	EQU	2	; Pin #2, Reset Gate, side B
SWA_L	EQU	0
SWA_H	EQU	4	; Pin #3, Summing Well, side A
SWB_L	EQU	0
SWB_H	EQU	8	; Pin #4, Summing Well, side B
S1AB_L	EQU	0
S1AB_H	EQU	$10	; Pin #5, Serial Phase #1, both sides
S2A_L	EQU	0
S2A_H	EQU	$20	; Pin #6, Serial Phase #2, side A
S2B_L	EQU	0
S2B_H	EQU	$40	; Pin #7, Serial Phase #2, side B
S3A_L	EQU	0
S3A_H	EQU	$80	; Pin #8, Serial Phase #3, side A
S3B_L	EQU	0
S3B_H	EQU	$100	; Pin #9, Serial Phase #3, side B
P3U_L	EQU	0
P3U_H	EQU	$200	; Pin #10, Parallel Phase #3, upper
P3D_L	EQU	0
P3D_H	EQU	$400	; Pin #11, Parallel Phase #3, lower
P2_L	EQU	0
P2_H	EQU	$800	; Pin #12, Parallel Phase #2
P1_L	EQU	0
P1_H	EQU	1	; Pin #13, Parallel Phase #1, clock driver board #1
TEST_L	EQU	0
TEST_H	EQU	2

; Define the voltages
RG_HI	EQU	$FFF	;+10 Volts, +12site, 10 is 4V below Vrg
RG_LO	EQU	$800	; 0  Volts
SW_HI	EQU	$c00	;+5  Volts
SW_LO	EQU	$400	;-5  Volts
S_HI	EQU	$c00	;+5  Volts
S_LO	EQU	$266	;-7  Volts
P_LO	EQU	$100	;~-9
P_HI	EQU	$b99	;~4.5
P3_LO	EQU	$266    ;-7  	
P3_HI	EQU	$d33	;~6.5  Volts
;
;P_HI	EQU	$B25	;+4  Volts
;P3_LO	EQU	0	;-9  Volts ph change
;P3_HI	EQU	$D00	; 6  Volts
;P_LO	EQU	0	;-10 Volts
;P3_HI	EQU	$C80	;+5  Volts	
;P3_LO	EQU	$180	;-8  Volts
;P_HI	EQU	$9E0	;+2  Volts old jamie
;P_HI	EQU	$B20	;+5  Volts ph change


;  ***  Definitions for Y: memory waveform tables  *****
; NON MPP clocking
PARALLEL DC	PARA_FLUSH-PARALLEL-2
;DO I HAVE TO SET THE SERIALS FIRST BEFORE STARTING PARALLEL SHIFT
;OR ARE THEY SET IN THE SERIAL CLEAR
;ASSUME P1 P2 ARE HIGH AND P3 LOW DURING INTEGRATION OR SERIAL 
;	DC	BD2+S_DELAY+S1AB_H+S2A_L+S3A_L+SWA_L+RGA_L+S2B_L+S3B_L+SWB_L+RGB_L                  ;0
;	DC	VIDEO+$000000+%1110100	; Change nearly everything
	DC	BD3+P_DELAY+P1_L                                                                    ;1
	DC	BD2+P_DELAY+S1AB_H+S2A_L+S3A_L+SWA_L+RGA_L+S2B_L+S3B_L+SWB_L+RGB_L+P2_H+P3U_H+P3D_H ;2
	DC	BD2+P_DELAY+S1AB_H+S2A_L+S3A_L+SWA_L+RGA_L+S2B_L+S3B_L+SWB_L+RGB_L+P2_L+P3U_H+P3D_H ;3
	DC	BD3+P_DELAY+P1_H                                                                    ;4
	DC	BD2+P_DELAY+S1AB_H+S2A_L+S3A_L+SWA_L+RGA_L+S2B_L+S3B_L+SWB_L+RGB_L+P2_L+P3U_L+P3D_L ;5
	DC	BD2+P_DELAY+S1AB_H+S2A_L+S3A_L+SWA_L+RGA_L+S2B_L+S3B_L+SWB_L+RGB_L+P2_H+P3U_L+P3D_L ;6

; NON MPP clocking
; set serials high for flush
PARA_FLUSH DC	SERIAL_IDLE-PARA_FLUSH-2
	DC	BD3+P_DELAY+P1_L                                                                    ;1
	DC	BD2+P_DELAY+S1AB_H+S2A_H+S3A_H+SWA_H+RGA_H+S2B_H+S3B_H+SWB_H+RGB_H+P2_H+P3U_H+P3D_H ;2
	DC	BD2+P_DELAY+S1AB_H+S2A_H+S3A_H+SWA_H+RGA_H+S2B_H+S3B_H+SWB_H+RGB_H+P2_L+P3U_H+P3D_H ;3
	DC	BD3+P_DELAY+P1_H                                                                    ;4
	DC	BD2+P_DELAY+S1AB_H+S2A_H+S3A_H+SWA_H+RGA_H+S2B_H+S3B_H+SWB_H+RGB_H+P2_L+P3U_L+P3D_L ;5
	DC	BD2+P_DELAY+S1AB_H+S2A_H+S3A_H+SWA_H+RGA_H+S2B_H+S3B_H+SWB_H+RGB_H+P2_H+P3U_L+P3D_L ;6

; Video processor bit definition
;	     xfer, A/D, integ, Pol+, Pol-, DCrestore, rst   (1 => switch open)
SERIAL_IDLE
	DC	SSKIP-SERIAL_IDLE-2
;	DC	BD3+S_DELAY+P1_H        ; do I need this
	DC	BD2+S_DELAY+S1AB_H+S2A_L+S3A_H+SWA_L+RGA_H+S2B_H+S3B_L+SWB_L+RGB_H+P2_H+P3U_L+P3D_L
	DC	VIDEO+$000000+%1110100	; Change nearly everything
	DC	BD2+S_DELAY+S1AB_L+S2A_L+S3A_H+SWA_L+RGA_H+S2B_H+S3B_L+SWB_L+RGB_H+P2_H+P3U_L+P3D_L
	DC	BD2+S_DELAY+S1AB_L+S2A_H+S3A_H+SWA_H+RGA_L+S2B_H+S3B_H+SWB_H+RGB_L+P2_H+P3U_L+P3D_L
	DC	BD2+S_DELAY+S1AB_L+S2A_H+S3A_L+SWA_H+RGA_L+S2B_L+S3B_H+SWB_H+RGB_L+P2_H+P3U_L+P3D_L
;	DC	SXMIT			; Transmit A/D data to host
	DC	VIDEO+$000000+%1110111	; Stop resetting integrator
	DC	VIDEO+$000000+%1110111	; Analog settling delay
	DC	VIDEO+$500000+%0000111	; Integrate for 1 microsec
	DC	VIDEO+$000000+%0011011	; Stop Integrate
	DC	BD2+S_DELAY+S1AB_H+S2A_H+S3A_L+SWA_H+RGA_L+S2B_L+S3B_H+SWB_H+RGB_L+P2_H+P3U_L+P3D_L
	DC	BD2+S_DELAY+S1AB_H+S2A_L+S3A_L+SWA_L+RGA_L+S2B_L+S3B_L+SWB_L+RGB_L+P2_H+P3U_L+P3D_L
	DC	VIDEO+$000000+%0011011	; Delay for signal to settle
	DC	VIDEO+$000000+%0011011	; Delay for signal to settle
	DC	VIDEO+$500000+%0001011	; Integrate for another microsec
	DC	VIDEO+$000000+%0011011	; Stop integrate, A/D is sampling


; Serial clocking waveform for skipping
SSKIP   DC	DACS-SSKIP-2
;	DC	BD3+S_DELAY+P1_H        ; do I need this
	DC	BD2+S_DELAY+S1AB_H+S2A_L+S3A_H+SWA_L+RGA_H+S2B_H+S3B_L+SWB_L+RGB_H+P2_H+P3U_L+P3D_L
	DC	BD2+S_DELAY+S1AB_L+S2A_L+S3A_H+SWA_L+RGA_H+S2B_H+S3B_L+SWB_L+RGB_H+P2_H+P3U_L+P3D_L
	DC	BD2+S_DELAY+S1AB_L+S2A_H+S3A_H+SWA_H+RGA_L+S2B_H+S3B_H+SWB_H+RGB_L+P2_H+P3U_L+P3D_L
	DC	BD2+S_DELAY+S1AB_L+S2A_H+S3A_L+SWA_H+RGA_L+S2B_L+S3B_H+SWB_H+RGB_L+P2_H+P3U_L+P3D_L
	DC	BD2+S_DELAY+S1AB_H+S2A_H+S3A_L+SWA_H+RGA_L+S2B_L+S3B_H+SWB_H+RGB_L+P2_H+P3U_L+P3D_L
	DC	BD2+S_DELAY+S1AB_H+S2A_L+S3A_L+SWA_L+RGA_L+S2B_L+S3B_L+SWB_L+RGB_L+P2_H+P3U_L+P3D_L

; Initialization of clock driver and video processor DACs and switches
DACS	DC	END_DACS-DACS-1
	DC	(BD2<<8)+RG_HI		; RGA High
	DC	(BD2<<8)+(1<<14)+RG_LO	; RGA Low
	DC	(BD2<<8)+(2<<14)+RG_HI	; RGB High
	DC	(BD2<<8)+(3<<14)+RG_LO	; RGB Low

	DC	(BD2<<8)+(4<<14)+SW_HI	; SWa High
	DC	(BD2<<8)+(5<<14)+SW_LO	; SWa Low
	DC	(BD2<<8)+(6<<14)+SW_HI	; SWb High
	DC	(BD2<<8)+(7<<14)+SW_LO	; SWb Low

	DC	(BD2<<8)+(8<<14)+S_HI	; S1ab High
	DC	(BD2<<8)+(9<<14)+S_LO	; S1ab Low
	DC	(BD2<<8)+(10<<14)+S_HI	; S2a High
	DC	(BD2<<8)+(11<<14)+S_LO	; S2a Low
	DC	(BD2<<8)+(12<<14)+S_HI	; S2b High
	DC	(BD2<<8)+(13<<14)+S_LO	; S2b Low
	DC	(BD2<<8)+(14<<14)+S_HI	; S3a High
	DC	(BD2<<8)+(15<<14)+S_LO	; S3a Low
	DC	(BD2<<8)+(16<<14)+S_HI	; S3b High
	DC	(BD2<<8)+(17<<14)+S_LO	; S3b Low

	DC	(BD2<<8)+(18<<14)+P3_HI	; P3u High
	DC	(BD2<<8)+(19<<14)+P3_LO	; P3u Low
	DC	(BD2<<8)+(20<<14)+P3_HI	; P3D High
	DC	(BD2<<8)+(21<<14)+P3_LO	; P3D Low
	DC	(BD2<<8)+(22<<14)+P_HI	; P2 High
	DC	(BD2<<8)+(23<<14)+P_LO	; P2 Low

	DC	(BD2<<8)+(24<<14)+P_HI	; P1 High
	DC	(BD2<<8)+(25<<14)+P_LO	; P1 Low
	DC	(BD2<<8)+(26<<14)+P_HI	; Test High
	DC	(BD2<<8)+(27<<14)+P_LO	; Test Low

; Set gain and integrator speed. x 9.5 gain, fast integrate
	DC	$0c3fdd			; Gain, integrate speed, board #0
;	DC	$0c3fee			; Gain, integrate speed, board #0

;	DC	$0c3f77			; Gain, integrate speed, board #0 x1
;	DC	$0c3fbb			; Gain, integrate speed, board #0 x2
;	DC	$0c3fdd			; Gain, integrate speed, board #0 x4.75
;	DC	$0c3fee			; Gain, integrate speed, board #0 x9

; Input offset voltages for DC coupling. Target is U4#6 = 24 volts
	DC	$0c08a0			; Input offset, ch. A
	DC	$0c8b00			; Input offset, ch. B

; Output offset voltages to get around 1000 DN A/D units on a dark frame
;	values used for meltdown
;	DC	$0c4a90			; Output video offset, ch. A
;	DC	$0cce70			; Output video offset, ch. B 
; dec sdsu values
;	DC	$0c4af2			; Output video offset, ch. A
;	DC	$0cce7a			; Output video offset, ch. B
; new values feb22 correct for ac coupled
;	DC	$0c4825			; Output video offset, ch. A
;	DC	$0ccfff			; Output video offset, ch. B
; new values feb22 correct for ac coupled, with zero ramp
;	DC	$0c4810			; Output video offset, ch. A
;	DC	$0ccfff			; Output video offset, ch. B
; new values, dc coupled with video clamped during parallel
;	DC	$0c4800			; Output video offset, ch. A
;	DC	$0ccfff			; Output video offset, ch. B
; newer values, dc coupled with video clamped during parallel
;	DC	$0c4803			; Output video offset, ch. A
;	DC	$0ccc00			; Output video offset, ch. B
; sdsu video card, dc coupled with video clamped during parallel
;	DC	$0c4b00			; Output video offset, ch. A
	DC	$0c4a00			; Output video offset, ch. A
	DC	$0cce00			; Output video offset, ch. B
;	DC	$0cc790			; Output video offset, ch. B
;	DC	$0c4500			; Output video offset, ch. A
;	DC	$0cc000			; Output video offset, ch. B

	
; DC bias voltages for the CCD chip
;	as i found them		
;	DC	$0d0c33			; Vod #1 = 24.30 V, pin #1
;	DC	$0d4c36			; Vod #2 = 24.30 V, pin #2
;	DC	$0d8a20			; Vrd = 14.00 V, pin #3, converts to 14.45 
;	DC	$0d0c73			; Vod #1 = 25.0 V, pin #1
;	DC	$0d4c73			; Vod #2 = 25.0 V, pin #2
;	DC	$0d8a60			; Vrd = 15.00 V, pin #3 ,dont exceed 16 = bbb
;	DC	$0dcbbb			; Vofd = 16 V, pin #4
;	DC	$0f84cc			; Vlga = -4.0 V pin #11
;	DC	$0fc4cc			; Vlgb = -4.0 V pin #12
; DC bias voltages for the CCD chip
	DC	$0d0c73			; Vod #1 = 25.0 V, pin #1
	DC	$0d4c73			; Vod #2 = 25.0 V, pin #2
	DC	$0d8a60			; Vrd = 15.00 V, pin #3 ,dont exceed 16 = bbb
	DC	$0dcd00			; Vofd = 16 V, pin #4  ,converts to 17.1
	DC	$0f84c4			; Vlga = -4.0 V pin #11 
	DC	$0fc4c4			; Vlgb = -4.0 V pin #12
END_DACS

; Check for Y: data memory overflow
        IF	@CVS(N,*)>$80
        WARN    'Application Y: data memory is too large!' ; Make sure Y:
	ENDIF						   ;  will not overflow

;  The fast serial code with the circulating address register must start on
;    a boundary that is a multiple of the address register modulus. 
	IF	DOWNLOAD
	ORG	Y:$80,Y:$80		; Download address
	ELSE
	ORG     Y:$80,P:(2*APL_NUM-1)*$100+APL_LEN+$A0	; EEPROM address
	ENDIF

; Fast Serials readout for single amp on RC chip
;	     xfer(01), A/D(01), integ, Pol+, Pol-, DCclamp, rst   (1 => switch open)
SERIAL	DC	BD2+S_DELAY+S1AB_L+S2A_H+S3A_L+SWA_L+RGA_H+S2B_H+S3B_L+SWB_L+RGB_H+P2_H+P3U_L+P3D_L
	DC	VIDEO+$000000+%0011011	; settle before sample
	DC	VIDEO+$000000+%1110100	; xfer(pix n-1),a/d(pix n),pol,dcclamp,rst 
	DC	BD2+S_DELAY+S1AB_L+S2A_H+S3A_L+SWA_L+RGA_H+S2B_H+S3B_L+SWB_L+RGB_H+P2_H+P3U_L+P3D_L
	DC	BD2+S_DELAY+S1AB_L+S2A_H+S3A_H+SWA_H+RGA_L+S2B_H+S3B_H+SWB_H+RGB_L+P2_H+P3U_L+P3D_L
	DC	BD2+S_DELAY+S1AB_L+S2A_L+S3A_H+SWA_H+RGA_L+S2B_L+S3B_H+SWB_H+RGB_L+P2_H+P3U_L+P3D_L
	DC	SXMIT			; Transmit A/D data (pix n-1) to host
	DC	VIDEO+$000000+%0010110	; dcclamp off, pol+
	DC	VIDEO+$000000+%0010111	; reset off
	DC	VIDEO+$000000+%0010111	; Analog settling delay
	DC	VIDEO+$500000+%0000111	; Integrate for 2 microsec 
	DC	VIDEO+$000000+%0010011	; Stop Integrate
	DC	VIDEO+$000000+%0011011	; pol+
	DC	BD2+S_DELAY+S1AB_H+S2A_L+S3A_H+SWA_H+RGA_L+S2B_L+S3B_H+SWB_H+RGB_L+P2_H+P3U_L+P3D_L
	DC	BD2+S_DELAY+S1AB_H+S2A_L+S3A_L+SWA_L+RGA_L+S2B_L+S3B_L+SWB_L+RGB_L+P2_H+P3U_L+P3D_L
        DC	VIDEO+$000000+%0011011  ; Delay for signal to settle
	DC	VIDEO+$000000+%0011011	; Delay for signal to settle
	DC	VIDEO+$500000+%0001011	; Integrate for another 2 microsec
	DC	VIDEO+$000000+%0011011	; Stop integrate, A/D is sampling
; B amp readout
;SERIAL	DC	BD2+S_DELAY+S1AB_H+S2A_L+S3A_H+SWA_L+RGA_H+S2B_L+S3B_H+SWB_L+RGB_H+P2_H+P3U_L+P3D_L
;	DC	VIDEO+$000000+%0011011	; settle before sample
;	DC	VIDEO+$000000+%1110100	; xfer(pix n-1),a/d(pix n),pol,dcclamp,rst 
;	DC	BD2+S_DELAY+S1AB_L+S2A_L+S3A_H+SWA_L+RGA_H+S2B_L+S3B_H+SWB_L+RGB_H+P2_H+P3U_L+P3D_L
;	DC	BD2+S_DELAY+S1AB_L+S2A_H+S3A_H+SWA_H+RGA_L+S2B_H+S3B_H+SWB_H+RGB_L+P2_H+P3U_L+P3D_L
;	DC	BD2+S_DELAY+S1AB_L+S2A_H+S3A_L+SWA_H+RGA_L+S2B_H+S3B_L+SWB_H+RGB_L+P2_H+P3U_L+P3D_L
;	DC	SXMIT			; Transmit A/D data (pix n-1) to host
;	DC	VIDEO+$000000+%0010110	; dcclamp off, pol+
;	DC	VIDEO+$000000+%0010111	; reset off
;	DC	VIDEO+$000000+%0010111	; Analog settling delay
;	DC	VIDEO+$500000+%0000111	; Integrate for 2 microsec 
;	DC	VIDEO+$000000+%0010011	; Stop Integrate
;	DC	VIDEO+$000000+%0011011	; pol+
;	DC	BD2+S_DELAY+S1AB_H+S2A_H+S3A_L+SWA_H+RGA_L+S2B_H+S3B_L+SWB_H+RGB_L+P2_H+P3U_L+P3D_L
;	DC	BD2+S_DELAY+S1AB_H+S2A_L+S3A_L+SWA_L+RGA_L+S2B_L+S3B_L+SWB_L+RGB_L+P2_H+P3U_L+P3D_L
;       DC	VIDEO+$000000+%0011011  ; Delay for signal to settle
;	DC	VIDEO+$000000+%0011011	; Delay for signal to settle
;	DC	VIDEO+$500000+%0001011	; Integrate for another 2 microsec
;	DC	VIDEO+$000000+%0011011	; Stop integrate, A/D is sampling
END_SERIAL			

; Serials for single readout of 0 amp, for amp 1 switch S2's and S3's
	;works for amp A on the RC chip
;SERIAL	DC	BD2+S_DELAY+S1AB_H+S2A_L+S3A_L+SWA_L+RGA_H+S2B_L+S3B_L+SWB_L+RGB_H+P2_H+P3U_L+P3D_L
;	DC	VIDEO+$000000+%1110100	; Change nearly everything
;	DC	BD2+S_DELAY+S1AB_H+S2A_L+S3A_L+SWA_L+RGA_L+S2B_L+S3B_L+SWB_L+RGB_L+P2_H+P3U_L+P3D_L
;	DC	BD2+S_DELAY+S1AB_H+S2A_L+S3A_H+SWA_H+RGA_L+S2B_L+S3B_H+SWB_H+RGB_L+P2_H+P3U_L+P3D_L
;	DC	BD2+S_DELAY+S1AB_L+S2A_L+S3A_H+SWA_H+RGA_L+S2B_L+S3B_H+SWB_H+RGB_L+P2_H+P3U_L+P3D_L
;	DC	BD2+S_DELAY+S1AB_L+S2A_H+S3A_H+SWA_H+RGA_L+S2B_H+S3B_H+SWB_H+RGB_L+P2_H+P3U_L+P3D_L
;	DC	BD2+S_DELAY+S1AB_L+S2A_H+S3A_L+SWA_H+RGA_L+S2B_H+S3B_L+SWB_H+RGB_L+P2_H+P3U_L+P3D_L
;	DC	BD2+S_DELAY+S1AB_H+S2A_H+S3A_L+SWA_H+RGA_L+S2B_H+S3B_L+SWB_H+RGB_L+P2_H+P3U_L+P3D_L
;	DC	BD2+S_DELAY+S1AB_H+S2A_L+S3A_L+SWA_H+RGA_L+S2B_L+S3B_L+SWB_H+RGB_L+P2_H+P3U_L+P3D_L
;	DC	SXMIT			; Transmit A/D data to host
;	DC	VIDEO+$000000+%1110111	; Stop resetting integrator
;	DC	VIDEO+$000000+%1110111	; Analog settling delay
;	DC	VIDEO+$500000+%0000111	; Integrate for 1 microsec
;	DC	VIDEO+$000000+%0011011	; Stop Integrate
;	DC	BD2+S_DELAY+S1AB_H+S2A_L+S3A_L+SWA_L+RGA_L+S2B_L+S3B_L+SWB_L+RGB_L+P2_H+P3U_L+P3D_L
;	DC	VIDEO+$000000+%0011011	; Delay for signal to settle
;	DC	VIDEO+$000000+%0011011	; Delay for signal to settle
;	DC	VIDEO+$500000+%0001011	; Integrate for another microsec
;	DC	VIDEO+$000000+%0011011	; Stop integrate, A/D is sampling
;END_SERIAL


; Check for overflow in the EEPROM case
	IF !DOWNLOAD
		IF	@CVS(N,@LCV(L))>(2*APL_NUM+1)*$100
	WARN    'EEPROM overflow!'	; Make sure next application
		ENDIF			;  will not be overwritten
	ENDIF

	ENDSEC		; End of section TIM

;  End of program
	END