The camera board contains the clamp and hold circuitry, the CCD clock drivers, a number of power supplies to generate the DC biases required by the CCD, and a temperature sensing circuit. The CCD is directly mounted on the board, which has a slot milled to accept the CCD cold finger. All logic lines coming onto the board are buffered with inverting schmitt triggers to minimize cross-talk in the cable.
Clock drivers
High speed MOSFET clock drivers were used to generate all the clocks. Since the logic input to these clock drivers is referred to the lowermost supply, the 5V CMOS/TTL input signal is level-shifted using a capacitive coupling scheme. The advantage of this technique over the traditional transistor level shifter approach (e.g. Cookbook camera) is that the quiescent power dissipation is much lower, and the signal rise/fall time is faster. The only disadvantage of this approach is that one must select the clock logic in such a way that when the input coupling capacitor relaxes to its DC level that the clock will be in the state desired for the quiescent level. Also, there is a finite amount of time in which the clock can remain in the (non-quiescent) level which is governed by the RC time constant of the coupling-capacitor/tie-up(down)-resistor combination. The selected clock drivers should easily be capable of driving the load capacitance of the KAF1602 chip without increasing the vertical clock cycle time.
Since horizontal phases H1 and H2 are complementary (H1 goes low when H2 goes high and vice-versa), a MOSFET driver with a single inverting and a single non-inverting output was used. The cross-over of the clocks can be precisely adjusted by trimming resistor R48 (this introduces a small delay between the two clock inputs). The useful adjustment range is several ns. Similarly, V1 and V2 are complementary during clocking so they share the same timing line. However, during integration both V1 and V2 are low so a separate line must be used to enable the V2 signal line into the clock driver. Since this disable signal does not need to switch rapidly, one of the unused switches on U12 (ADG453) was used to provide an enable for the V2 signal line. The crossover between the complementary V1 and V2 phases is adjusted by trimming resistor R53. Note that if separate logic lines were used for all the clocks, this level of control over the crossover of the complementary phases could not be guaranteed due to jitter between the outputs of MCU. Optimally, the clock timings should be set so that the complementary phases cross at their 50% levels.
Temperature sensing circuit
The temperature sensor used is an LM335 linear, centigrade-scale diode sensor IC with 10mV/°C output. The sensor should be epoxied into a hole drilled into the side of the cold finger, as close as possible to the CCD. The sensing circuit includes an adjustable precision reference to set the zero-point of the sensor. A nominally correct calibration would have 2.083V appearing at the output of the OP213 (pin 1 of U9A) buffer op-amp; this is adjusted by trimming R32. Setting the zero-point voltage to this value is sufficient to obtain ±1°C accuracy.
The temperature scale is adjusted by trimming R36 which changes the gain of the output buffer (U9B). With the zero-point set, one simply trims R36 until the correct temperature is displayed on the controller's LCD monitor. The gain of op-amp U9B is set so that the 1024 ADU range of the ADC corresponds to the range -64.0°C to +38.3°C (0.1°C per ADU).
Supplies and DC-biases
The ±15.5V (minimum) input to the board is regulated down to ±15V by a pair of low-dropout linear regulators (U3 and U5). Since the CCD clocks and biases require little continuous current, the 8 biases and clock levels are generated by two quad op-amps (LM2902; U6 and U7). The bias levels are set by the voltage dividers on the input of these op-amps, configured as voltage followers. A resistive voltage-divider is used for the 9V guard-bias instead because it requires almost no current.
Clamp and hold circuit
Correlated double sampling is achieved by using a simple clamp and hold circuit similar to that used in the Audine camera. The CCD video output is AC coupled by capacitor C1 and tied near ground by resistor R1. This removes most of the large DC bias (~9V) on the CCD output signal. The time constant R1*C1 was selected so that less than 1/216 droop in the voltage would occur over the readout period (several µs), assuming a saturated video-level (worst case droop). The AD825 JFET input op-amp (U1) provides a fixed gain of 9.2; it is used in non-inverting configuration to allow for a moderately high input impedance of 10 kOhms (note that the gain resistors must be kept small to maintain the bandwidth - the impedance in inverting configuration would only be 1kOhm). All of the gain is in the first stage to minimize noise in the electronic chain.
The amplified signal is AC-coupled to a second AD825 op-amp (U2) through a moderately low capacitance (3300 pF, C6). The signal can be clamped to ground by shorting C6 through a fast analog switch (ADG453, U12). The signal is clamped to ground following the CCD output amplifier reset and before the photo-charge is shifted into the CCD output amplifier. In this way, any signal following the toggling of the clamp is referred with respect to the CCD reset level. The ADG453 was selected for its very low on-resistance (4Ohms). A low on-resistance is desirable because the discharge time of C6 through the switch determines the settling time of the clamp circuit. With the selected components, A 10V reset level will discharge down to (10/216)V in 150 ns. For comparison, a typical analog switch has an on-resistance of 35 Ohms and would lead to a settling time of 1.3 µs. Of course, the reset level is usually much closer to ground than 10V, so this is a worst case example. In addition to the low on-resistance, the off resistance of the switch, as well as the input impedance of the op-amp must be high to avoid sagging of the video level during the digitization period. A high off-resistance is inherent to most analog switches, the high impedance criterion for the op-amp is satisfied by selecting a JFET input device.
CCD output amplifier turn-off
The +15V supply to the CCD output amplifier drain can be reduced to 7.5V during integration. This prevents the electroluminescence in the CCD output amplifier from contaminating the photo-pixels neighbouring the output structure. The supply is switched by a pair of switches on the ADG453 (U12).